The inverting amplifier's input impedance, and where its gain error comes from

The input impedance is Rin. Not more, not less

In an inverting amplifier, the op-amp's negative feedback holds the inverting input at the same potential as ground (virtual ground). From the signal source's point of view, the far end of Rin is tied to ground, so the input impedance is exactly Rin — no matter how high the op-amp's own input impedance is.

Connect a source with output resistance R_s and R_s adds in series with Rin, dropping the gain to -Rf / (Rin + R_s). Feed a sensor with R_s = 10kΩ into a circuit with Rin = 10kΩ and the gain is half the design value. Keeping the error under 1% needs Rin ≥ 100 × R_s — for R_s = 10kΩ that's Rin = 1MΩ, and pushing Rin that high runs into the noise and stray-capacitance issues discussed below.

If the source impedance is high (a few kΩ or more), use a non-inverting amplifier instead. Its input impedance is the op-amp's own input impedance (10^12 Ω or more for CMOS), so it doesn't load the source at all. Reach for inverting when the source is low-impedance (an op-amp output, a DAC), when you want to sum several inputs, or when you want to sidestep the common-mode input range limits of a non-inverting stage.

Error from finite open-loop gain

An ideal op-amp has infinite open-loop gain A, but real parts run 10^5-10^7 DC and roll off at -20dB/decade with frequency. With finite gain, the closed-loop gain becomes 1 / (1 + 1/(A·β)) times the design value. β is the feedback factor — for an inverting stage, β = Rin / (Rin + Rf) — and 1/β is the noise gain = 1 + Rf/Rin.

For a gain of -10 (Rf = 100kΩ, Rin = 10kΩ), the noise gain is 11. An op-amp with GBW = 1MHz has A = 100 at 10kHz, so the loop gain A·β ≈ 100/11 ≈ 9. The error is 1/(1+9) = 10%. At 1kHz, A = 1000 and the error is 1.1%. At 100Hz, 0.1%.

So a gain-of-10 stage built with a 1MHz-GBW op-amp already has a 1% error at 1kHz. The usual -3dB bandwidth figure of "GBW / noise gain = 91kHz" is the point where the response is already down 30% — the band where you can trust the gain is 1/100 of that or less.

To keep the error under 0.1% at a given frequency you need A·β ≥ 1000 there, i.e. A ≥ 1000 × noise gain. For a gain of 10 at 10kHz that means A ≥ 11,000, so GBW ≥ 110MHz — beyond a general-purpose op-amp and into high-speed territory.

Resistor tolerance, offset, and bias current

Resistor tolerance. Since gain is Rf/Rin, two ±1% resistors give a worst case of ±2%; two ±0.1% resistors give ±0.2%. Same logic as a divider. Temperature coefficient also affects the ratio, so use resistors from the same series.

Input offset voltage. V_os appears at the output multiplied by the noise gain. With V_os = 1mV and a noise gain of 11, that's 11mV at the output, or 1.1mV referred to the input for a gain of 10. If the input signal is only 10mV, that's an 11% error. Where precision matters, choose an op-amp with low V_os (100µV or less, or 5µV or less for a chopper-stabilized part).

Input bias current. The current I_b flowing into the inverting input passes through Rf ∥ Rin, and the resulting voltage drop becomes an offset. For a bipolar-input op-amp (I_b = 100nA) with Rf = 100kΩ, that's 100nA × 9.1kΩ ≈ 0.9mV. Adding a matching resistor (Rf ∥ Rin) from the non-inverting input to ground produces the same drop on both inputs and cancels it (only the offset current remains). CMOS or JFET inputs (I_b in the pA range) don't need this resistor — adding one there only adds thermal noise.

Feedback-resistor stray capacitance and the bandwidth ceiling

A stray capacitance C_f of 0.2-1pF from pads and traces sits in parallel with Rf. This forms a pole with Rf at f = 1/(2π·Rf·C_f), above which gain rolls off. With Rf = 100kΩ and C_f = 0.5pF that's 3.2MHz; with Rf = 1MΩ it drops to 320kHz — the stray capacitance sets the bandwidth before the op-amp's own bandwidth does.

In the other direction, the inverting input's own capacitance to ground (op-amp input capacitance plus wiring, 5-10pF) forms a pole with Rin ∥ Rf, adding phase lag in the feedback loop and becoming a source of oscillation. This is pronounced with a high-capacitance source such as a photodiode (tens to hundreds of pF), and is typically compensated by deliberately adding a few pF of C_f across Rf.

For these reasons, it's practical to keep Rf between 1kΩ and 100kΩ. Below 1kΩ, the op-amp output is heavily loaded driving Rf + Rin; above 100kΩ, stray capacitance and noise (40nV/√Hz at 100kΩ) start to dominate.

Checking the design with the calculator

The inverting amplifier calculator computes gain from Rf and Rin. As a design procedure, first set a floor for Rin from the source impedance (100x R_s), then check whether the target gain is achievable against a practical ceiling for Rf (around 100kΩ). If not, switch to non-inverting or split the gain across two stages.

Next, compute the loop gain at the frequency where accuracy matters from the GBW, and confirm the error is acceptable. Finally, refer offset and bias current to the input and compare against the smallest signal you need to measure.