The inverting amplifier's input impedance, and where its gain error comes from

The input impedance is Rin

In an inverting amplifier, negative feedback holds the inverting input at ground potential (virtual ground). From the source's side the far end of Rin is tied to ground, so the input impedance is exactly Rin.

A source with output resistance R_s adds it in series with Rin, so the gain drops to −Rf / (Rin + R_s). R_s = 10kΩ into Rin = 10kΩ gives half the design gain. An error under 1% needs Rin ≥ 100 × R_s, i.e. Rin = 1MΩ.

If the source impedance is a few kΩ or more, use a non-inverting amplifier, whose input impedance is the op-amp's own (10^12 Ω or more for CMOS). Choose inverting when the source is low-impedance (an op-amp output, a DAC) or when summing several inputs.

Error from finite open-loop gain

A real op-amp's open-loop gain A is 10^5–10^7 at DC and rolls off at −20dB/decade. The closed-loop gain deviates by about 1/(A·β), where β = Rin / (Rin + Rf) and 1/β is the noise gain = 1 + Rf/Rin. The deviation includes phase lag; the amplitude alone stays close to nominal until near the −3dB frequency.

For a gain of −10 (Rf = 100kΩ, Rin = 10kΩ) the noise gain is 11. With GBW = 1MHz, A = 100 at 10kHz and A·β ≈ 9, a deviation of about 11%; about 1.1% at 1kHz and 0.11% at 100Hz. At GBW / noise gain = 91kHz (the −3dB bandwidth), A·β = 1 and the amplitude is down 29%.

Staying within 0.1% needs A·β ≥ 1000, i.e. A ≥ 1000 × noise gain: for gain 10 at 10kHz, GBW ≥ 110MHz, beyond a general-purpose op-amp.

Resistor tolerance, offset, and bias current

Resistor tolerance. Gain is Rf/Rin, so two ±1% resistors give a worst case of ±2% (±0.2% for 0.1%). Use the same series, since temperature coefficient also acts on the ratio.

Input offset voltage V_os is multiplied by the noise gain. V_os = 1mV with a noise gain of 11 gives 11mV at the output, or 1.1mV at the input for gain 10, an 11% error on a 10mV signal. Where precision matters, choose a low-V_os op-amp (100µV or less, 5µV or less for a chopper-stabilized part).

Input bias current I_b flows through Rf ∥ Rin and drops a voltage. A bipolar-input op-amp (I_b = 100nA) with Rf = 100kΩ gives 100nA × 9.1kΩ ≈ 0.9mV. A matching Rf ∥ Rin resistor from the non-inverting input to ground makes the same drop on both inputs and cancels it (only the offset current remains). CMOS or JFET inputs (I_b in the pA range) don't need it.

Feedback-resistor stray capacitance and the bandwidth ceiling

A stray capacitance C_f (0.2–1pF) across Rf rolls gain off above f = 1/(2π·Rf·C_f): 3.2MHz for Rf = 100kΩ and C_f = 0.5pF, 320kHz for Rf = 1MΩ.

The inverting input's capacitance to ground (5–10pF) forms a pole with Rin ∥ Rf, and the phase lag in the loop can cause oscillation. With a photodiode (tens to hundreds of pF), compensate with a few pF of C_f across Rf.

Rf is practically 1kΩ to 100kΩ. Below 1kΩ the output is heavily loaded; above 100kΩ, stray capacitance and noise (40nV/√Hz at 100kΩ) dominate.

Checking the design with the calculator

The inverting amplifier calculator computes gain from Rf and Rin. If the gain doesn't fit between a floor for Rin (100x R_s) and a ceiling for Rf (around 100kΩ), use non-inverting or two stages. Then check the loop gain at the frequency that matters and the input-referred offset and bias current.