IBIS model waveform simulator

Load an IBIS model (.ibs) and run a transient analysis of driver IC → package → PCB trace (transmission line) → termination → receiver IC, showing the waveform at both ends. A model with [Diff_pin] can also be analysed as a differential pair (LVDS and similar), giving Vod and Vos waveforms and an eye diagram.
Nodal analysis with Newton-Raphson and backward Euler, plus Branin's method for the transmission line, all written from scratch (no external engine such as SPICE). Your file is processed inside the browser and never uploaded.

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You can also drag and drop a file here. A loaded model is kept only in your browser's local storage. Vendor IBIS models usually forbid redistribution, so none are bundled with this site — load your own .ibs. The demo model is fictitious synthetic data generated for this site (Public Domain / CC0) and contains a single-ended 3.3 V CMOS I/O plus an LVDS differential pair with [Diff Pin].

Device

Signalling

Corner

Driver pair

Receiver pair

Driver model

Receiver model

Package

Driver pin

Receiver pin

P/N skew ps

Driver signal

Bit rate Mbps

Bit pattern

Pattern

Repeat ×

Transition from

Transition scale ×

The 20–80 % slope of [Ramp] is converted to a full-swing transition time of dt / 0.6.

PCB trace

Specify by

Characteristic impedance Ω

Differential impedance Ω

Trace length mm

Propagation delay ps/mm

Trace resistance Ω

Termination

Series R at driver Ω

Termination at receiver

R across pair Ω

Termination R Ω

Vtt V

R1 → VCC Ω

R2 → GND Ω

Termination C pF

Extra C at receiver pF

Use this to add the parasitic capacitance of connectors, vias or test pads.

Analysis

Points per bit

Recalculate on every change

Circuit

Waveforms Drag to zoom the time axis, double-click to fit

Eye diagram at the receiver

Measurements (receiver)

Driver I-V characteristics

Pullup (load line while driving High) Pulldown (while driving Low) Clamps only

The horizontal axis is the pad voltage and the vertical axis is the current flowing out of the pad. The reciprocal of the slope is the effective output resistance.

What this simulator does, and where it stops

Circuit model

A one-dimensional circuit is assembled — driver die (C_comp and the I-V tables) → package (R_pkg + L_pkg in series, C_pkg to ground) → series resistor at the driver → transmission line → termination → receiver package → receiver die (C_comp and clamps) — and the nodal equations are solved for every node.

Numerical method

Time integration: backward Euler (unconditionally stable, fixed step)
Nonlinear elements: Newton-Raphson. I-V tables are interpolated piecewise-linearly and their slope feeds the Jacobian
Transmission line: a lossless delay line by Branin's (method of characteristics) approach. Travelling waves are kept in a history buffer, and any delay that is not an integer number of time steps is interpolated linearly
DC loss: the line is split into several segments with a series resistor between them
Initial state: the DC operating point is solved with Newton's method, then capacitor voltages, inductor currents and the travelling waves on the line are initialised

Which parts of IBIS are used

Keyword	How it is used
`[Pullup] / [Pulldown]`	The driver's nonlinear I-V, combined with the weights Ku(t) and Kd(t)
`[POWER_Clamp] / [GND_Clamp]`	ESD clamps. These are what limit overshoot and undershoot
`[Ramp]`	The 20–80 % dV/dt gives a transition time of dt / 0.6, and Ku/Kd then change linearly
`[Rising/Falling Waveform]`	When present, Ku(t) is back-calculated from the fixture load, giving a more realistic edge shape than [Ramp]
`C_comp`	Die capacitance
`[Package] / [Pin]`	R_pkg, L_pkg and C_pkg (or the per-pin values)
`[Diff_pin]`	The partner of a differential pair, the differential threshold vdiff and the P/N skew tdelay
`[Voltage Range] and similar`	Supply voltage and the reference voltage of each table
`Vinh / Vinl / Vmeas`	Receiver threshold checks and the reference for propagation delay

Differential mode

Models that carry [Diff_pin] let you pick "differential pair". The same [Model] is assigned to the P and N sides, two lanes driven with complementary Ku/Kd are set up, and both are solved together as one circuit. The displayed Vod is P − N and Vos is (P + N) / 2.

The line is treated as two independent conductors of odd-mode impedance Zdiff/2. The coupling between them is not solved, so the differential mode is sound but the common-mode impedance comes out simpler than reality.
Termination can be a single resistor across the pair (100 Ω for LVDS), a split termination (R/2 ×2 with a midpoint capacitor), or a resistor to GND / Vtt on each line.
Adding P/N skew shows part of the differential signal converting into common mode. If [Diff_pin] carries tdelay, it is loaded as the initial value.
The logic threshold is decided by vdiff in [Diff_pin] (whether |Vod| exceeds it). The single-ended Vinh / Vinl are not used in differential mode.
For current-mode drivers such as LVDS, Vod may be right while Vos (the common-mode voltage) disagrees with the datasheet. IBIS [Pullup] / [Pulldown] are per-conductor tables, so they cannot express the internal common-mode feedback. The Vos shown here is what the model says, not what the device can do.

Deliberate simplifications

This is the single-waveform method assuming Ku + Kd = 1, not the two-waveform method that solves Ku and Kd independently from both the rising and the falling waveform.
With a model that only has [Ramp], Ku/Kd change linearly, so edges come out slightly more angular than the rounded ones you would measure.
The transmission line is lossless plus a DC resistance. Skin effect, dielectric loss and dispersion are not included, so over long distances or at several Gbps the waveform looks cleaner than reality.
Crosstalk, power/ground bounce (SSO) and asymmetric return paths are not handled.
[Driver Schedule], [Submodel] and [External Model] (IBIS-AMI) are not supported.
A differential pair is solved as two independent lines, so inter-line coupling and differential crosstalk are not included.
The supply voltage is treated as an ideal voltage source.

This tool is meant for getting a feel for the trends — reflections, ringing, and how much the termination style matters. For shipping decisions or compliance testing, use your vendor's own SI tool.

Related calculators

Characteristic impedance — microstrip (outer layer) / Convert trace length to delay time / Convert delay time to trace length / Lumped or distributed