Characteristic impedance — microstrip (outer layer)

Characteristic impedance of a trace on an outer layer. Outer-layer routing has a lower effective permittivity — less loss and less delay — which is why it is preferred for fast signals. Single-ended 50 Ω: DDR data bus, DDR address bus Differential 75 Ω: analogue video Differential 85 Ω: USB, PCI Express Differential 90 Ω: DDR DQS and clock Differential 100 Ω: Ethernet, MDI, LVDS, MIPI

Trace width

Dielectric thickness

Trace spacing

SI prefixes accepted (4k7 / 1M / 10m / 220). Upper-case M = mega, lower-case m = milli

Single-ended

49.13Ω

Differential

91.34Ω

Advanced — Copper thickness, PCB relative permittivity

Copper thickness

PCB relative permittivity

εr

Derived values

Effective permittivity εeff: 2.71; 0.475 × εr + 0.67
Propagation delay: 5.49 ps/mm; Used for length matching
Capacitance per length: 0.112 pF/mm; TD / Z0
Inductance per length: 0.27 nH/mm; TD × Z0

A 1 ns skew corresponds to 182 mm of trace length (length matching rule of thumb).
Allowing the usual ±10% fabrication tolerance, the single-ended value lands between 44.22 and 54.04 Ω.

History

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Formula

Z0 (single-ended): (60/√εeff) × ln(4h/(0.67π×(0.8W+T)))
Zdiff (differential): 2×Z0 × (1−0.48×exp(−0.96×S/h))
εeff ≈ 0.475×εr + 0.67

Design notes

Fast digital and RF traces have to hit a specified characteristic impedance. A mismatch reflects the signal, and reflections are what show up later as errors and intermittent faults.

Standard impedances by interface:
• Single-ended 50 Ω: DDR data and address buses, SPI
• Differential 75 Ω: analogue video (SDI)
• Differential 85 Ω: USB 2.0, PCI Express
• Differential 90 Ω: DDR DQS and clock
• Differential 100 Ω: gigabit Ethernet, LVDS, MIPI

Fabrication tolerance is normally ±10%. Settle the nominal here, then hand it to the board house as a controlled-impedance requirement.

When you need this

For checking, before you commit to controlled impedance with your fabricator, whether 50Ω single-ended or 100Ω differential is realistic on the stack-up you have. It avoids fixing a trace width first and being told afterwards that the dielectric height will not support it.

Scope

Microstrip (outer layer) only. It assumes a single reference plane below the trace. It does not apply to stripline, where the trace sits between two planes.
This is the IPC-2141 approximation. It is good to a few percent for w/h roughly 0.1–3.0 and εr roughly 1–15. Very narrow or very wide traces drift further out.
Solder mask is not included. Mask over the trace raises the effective permittivity and pulls impedance down by 1–3Ω. Note also that masked and unmasked sections differ.
The trapezoidal etched cross-section is not included. Real traces are narrower on top than at the base, which is another few percent.

Always have your fabricator confirm the final trace width with their field solver. This calculator is for finding out roughly where you stand. ±10% is the normal manufacturing tolerance; asking for ±5% costs noticeably more.

Trace widths for 50Ω on FR-4 (εr = 4.3, 35µm copper)

Differential figures assume spacing s equal to trace width w. Confirm actual values with the calculator.
Dielectric height h	Width w	Single-ended	Differential (s = w)
0.1mm	0.12mm	about 55Ω	about 94Ω
0.1mm	0.14mm	about 51Ω	about 89Ω
0.1mm	0.16mm	about 47Ω	about 85Ω
0.2mm	0.25mm	about 59Ω	about 101Ω
0.2mm	0.30mm	about 53Ω	about 95Ω
0.2mm	0.35mm	about 49Ω	about 88Ω

Widening the gap s raises differential impedance. At roughly twice the trace width the coupling is weak enough that differential impedance approaches twice the single-ended value.

What matters in practice

Dielectric height dominates. Impedance depends on h roughly logarithmically. If h is too small, no achievable trace width will reach 50Ω. Check this while the stack-up is still being decided.
Keep the reference plane continuous. A slot or split under the trace breaks the assumption of a uniform plane. Impedance jumps, return current detours, and you have created an EMI source.
Differential impedance is set by the gap. It follows from the single-ended value plus the coupling between the pair. Changing pair spacing mid-route changes impedance at that point.
Copper weight matters too. Going to 2oz (70µm) increases the cross-section and drops impedance by 2–4Ω at the same width. Do not confuse signal-layer and plane-layer copper weights.

Frequently asked questions

My fabricator quotes a value a few ohms different. Who is right?

They are. Their 2D field solver accounts for the real stack-up, resin-to-glass ratio, solder mask and etch factor. This closed-form approximation omits mask and etching, so it reads a few percent high.

How much spacing do I need for 100Ω differential?

Get the single-ended value slightly above 50Ω first, then start with a gap of 1.5–2 times the trace width. Widening the pair does make it more susceptible to common-mode noise, so do not overdo it. Sweep the spacing here and take the smallest gap that reaches 100Ω.

What does controlled impedance add to the cost?

At ±10% the increment is small — essentially a test coupon and a measurement report. Asking for ±5% requires material selection and tighter process control and shows up clearly in the price. Design so that ±10% works.

How much does solder mask change things?

20–30µm of mask over the trace raises the effective permittivity and lowers impedance by 1–3Ω. If you are targeting 50Ω, have the fabricator set the width so that the masked condition lands on 50Ω.

Standards and references

IPC-2141A — Source of the approximation used here, including its range of validity.
IPC-2221B — General PCB design standard; conductor width and spacing.
IPC-6012 — Board performance specification; tolerance classes for controlled impedance.

Last updated: 2026-08-29