Propagation speed on a PCB from permittivity

How fast a signal travels on a board. The higher the permittivity, the slower it goes. A low-permittivity laminate gives less propagation delay, which is why it is preferred for high-speed signals such as 5G and mmWave.

PCB relative permittivity

εr

Propagation delay

6.912ps/mm

Propagation speed

0.1447mm/ps

History

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Formula

Propagation speed: v = c / √εr [m/s]
Propagation delay: TD = √εr / c [ps/mm]
Example: FR-4 (εr = 4.3) → about 14.5 ps/mm

Design notes

A signal on a printed circuit board travels more slowly than light. The speed follows from the relative permittivity (εr) of the laminate, and high-speed digital design uses it to budget trace delay.

Relative permittivity of common materials:
• FR-4 (general purpose): εr ≈ 4.2–4.8
• Rogers 4350B (high-speed): εr ≈ 3.48
• PTFE (microwave): εr ≈ 2.1

Use the ps/mm figure from this calculator when length-matching DDR or PCI Express.

When you need this

This is the first number you need when setting the length-matching tolerance for DDR, LVDS, PCIe or any other matched bus. Take the dielectric constant from the stack-up your fabricator sent you, and you have the picoseconds per millimetre that every later timing decision is built on.

What is being calculated

The speed of light reduced by the dielectric the signal travels through. Higher permittivity means slower propagation, so the delay t_pd rises with √εr.

Two outputs are given. ps/mm is how long a millimetre of trace costs you, which is what length matching and timing budgets are written in. mm/ps is the reciprocal, handy for converting a timing margin straight into a trace length.

Where this applies

This applies cleanly to inner layers (stripline), where the trace is surrounded by the same dielectric above and below, so the effective permittivity is simply εr.
It does not apply to surface layers (microstrip). Air sits above the trace, lowering the effective permittivity, so outer-layer signals travel roughly 10–15% faster. For surface traces use Trace length to delay, which reports both.
εr varies with frequency (dielectric dispersion). FR-4 is around 4.6–4.8 at 1MHz but drops to 4.2–4.4 at 1GHz. Always check at what frequency the datasheet value was measured.
Where the trace sits relative to the glass weave changes εr locally. Above about 10Gbps this glass-weave skew becomes a real contributor to differential pair skew.

Common laminate values

Permittivity at around 1GHz. Delay is the stripline (inner layer) figure.
Material	εr (typical)	Delay ps/mm	Per 100mm
FR-4 (standard)	4.2 – 4.6	6.8 – 7.2	about 690 ps
FR-4 (high Tg)	4.1 – 4.5	6.7 – 7.1	about 680 ps
Megtron 6	3.6 – 3.7	6.3 – 6.4	about 640 ps
Rogers 4350B	3.48	6.2	about 620 ps
Polyimide (flex)	3.2 – 3.5	6.0 – 6.2	about 610 ps
Air	1.0	3.34	about 334 ps

For mental arithmetic: FR-4 inner layers are about 7 ps/mm, outer layers about 6 ps/mm. That is usually enough to sanity-check a trace length during a review without opening a tool.

Worked example: DDR address line skew

Standard FR-4, and the stack-up gives εr = 4.3.
Entering 4.3 gives 6.912 ps/mm.
Suppose the timing budget allows 50ps of skew between address lines.
50 ps ÷ 6.912 ps/mm = about 7.2mm of allowed length difference.
Vias and package-internal routing eat into that, so aim for roughly half — ±3mm on the board — to stay safe.

Common mistakes

Length-matching traces that mix outer and inner layers. They travel at different speeds, so equal lengths are not equal times. Anything that changes layer must be matched in picoseconds.
Taking the datasheet εr at face value. A value measured at a low frequency is too high, so you overestimate delay and add serpentine routing you did not need.
Ignoring via delay. A via through a 1.6mm board costs roughly 10ps. On a net that changes layer several times this adds up.
Ignoring lot-to-lot variation. Nominally identical FR-4 varies by about ±5% between suppliers and lots, which is ±2.5% in delay.

Frequently asked questions

What propagation delay should I actually use for FR-4?

Start with 6.9–7.0 ps/mm for inner layers and 6.0–6.1 ps/mm for outer layers. If the design is tight, ask your fabricator for the effective permittivity of your specific stack-up — two laminates both called "FR-4" can differ noticeably depending on the resin-to-glass ratio.

Why are surface traces faster?

A microstrip has air above it. Part of the field travels through εr = 1, so the effective permittivity the trace sees is lower than the laminate value and the signal moves faster. The trade-off is that surface traces pick up and radiate noise more readily.

How do ps/mm and ps/inch relate?

Multiply by 25.4. FR-4 inner layers at 6.9 ps/mm is about 175 ps/inch. English-language references often quote the rule of thumb "150 ps/inch on outer layers, 180 ps/inch on inner layers".

What do I gain from a low-εr laminate?

Less delay, so you can route further within the same timing budget. Such materials usually also have a lower loss tangent, which reduces high-frequency loss. The cost is several times that of FR-4, so the usual approach is the cheapest material that meets the speed requirement.

Standards and references

IPC-2141A — Controlled impedance and high-speed design; propagation delay and effective permittivity.
IPC-4101 — Laminate specification; permittivity and Tg classes by material.
Howard Johnson, "High-Speed Digital Design" — Practical treatment of delay and stack-up.

Last updated: 2026-08-29