An LDO cannot sink current: where current injected through protection diodes goes

Source and sink: a regulator is one-way

An LDO places a PNP or P-channel MOSFET pass element between input and output, and an error amplifier decides how far it opens. The direction is input to output only, and when the output rises above the setpoint the most the LDO can do is close the pass element completely. It has no way to pull current out of the output to bring the voltage down. The only paths from the output to GND are the feedback divider (tens of µA) and, on some parts, a discharge FET that conducts only when EN is low.

A switching regulator with a diode (asynchronous) buck can only source too. A synchronous buck's low-side MOSFET conducts both ways, so the inductor current can go negative and return energy from the output to the input, but only in forced PWM.

Whether a regulator can sink depends not on LDO versus switcher but on whether the circuit has a path from the output to GND (or the input). With no such path, the only place injected current can go is the load.

Where trapped current goes: protection diodes

Nearly every IC pin has protection (ESD) diodes to VDD and GND. When the pin voltage exceeds VDD + 0.6V the upper diode turns on and current flows from the pin into the VDD rail. Typical cases: 5V logic driving a 3.3V IC input directly, a UART or I2C still connected to a board that is powered off, and a pull-up tied to a different supply.

The injected current can go to the LDO (which only closes), the output capacitor (only while charging), or the load. The rail rises until the load's absorption balances the injection. With one MCU asleep (50µA) as the load, 5V drive, V_F = 0.6V and a 220Ω series resistor R_s, V = 5 − 0.6 − 220Ω × 50µA ≈ 4.4V. The steady current is only 50µA; the problem is the voltage, not the current.

What happens at 4.4V

• Every part on the rail exceeds its absolute maximum rating. For 3.3V parts the limit is often 3.6V (radio modules, FPGA I/O) or 4.0V (many MCUs); 4.4V exceeds both. They may not fail at once, but lifetime shrinks and you are outside warranty.
• Latch-up at the injected pin. Current into a pin has its own absolute maximum (often ±5 to 20mA per pin); beyond it a parasitic thyristor fires and shorts VDD to GND. Limit the pin current itself with a series resistor.
• It will not power off (back-powering). If a USB-serial adapter left connected keeps feeding 2-4V through RX, the MCU does not reset and the next power-up can start from a strange state.
• Reverse flow into the LDO. The pass element's body diode points from output to input. With the input off and the output more than 0.6V above it, current flows backward through the LDO and lifts the input side. The allowed value is in the datasheet's "reverse current" entry.
• False power-good or supervisor results. The rail looks present, so the next supply starts or reset is released.

Whether it is contained depends on whether (V_drive − V_F − 3.3V) / R_s is at or below the load's minimum current; for 5V drive that is 1.1V / R_s. With power off (load current 0), no R_s contains it.

Can a switching regulator sink? Synchronous rectification and forced PWM

Push the same current into a synchronous buck and the control loop cuts the duty cycle; the average inductor current becomes 50µA − 5mA ≈ −5mA (output to input). The low-side MOSFET conducts throughout the off period and carries negative current, so the converter runs as a 3.3V-to-5V boost and the output stays at 3.3V. The returned power is 3.3V × 5mA ≈ 16mW. There are three conditions.

1. Forced PWM (FPWM, FCCM). In power-save modes (PFM, pulse skipping, auto mode) the low-side MOSFET turns off when inductor current reaches zero, so the result is the same as an LDO. Injection matters when the load is light, which is exactly when an auto-mode IC is in power-save. Choose a part whose MODE pin can force PWM.

2. The returned current has somewhere to go on the input side. It enters the input capacitor. If the input is the output of another LDO or an asynchronous converter with no other load, the input voltage rises and the problem just moves upstream.

3. Within the negative current limit. A forced-PWM IC has a negative current limit (often smaller than the positive one); a larger injection lets the output rise.

Circuits that add sinking

Adding a transistor alone does not work. You need a reference and an error amplifier to decide when and how much to conduct. Three options, cheapest first.

1. Create a path or limit the inflow. Raise the pin series resistor R_s so 1.1V / R_s is below the load's minimum current, or add a bleed resistor so the minimum load exceeds the injection. With R_s = 1kΩ you need 1.1mA or more of load, and a 3kΩ bleed resistor wastes 3.6mW continuously. R_s = 22kΩ works at 50µA, but with a 5pF input capacitance it forms a 110ns RC and is no use on fast signals. The fundamental fix is a logic IC with I_off (partial power-down) at the boundary, which blocks inflow when its supply is off.

2. Clamp from above with a shunt regulator (TL431). Connect the cathode to the rail and the anode to GND, and set REF with a divider slightly above 3.3V. R1 = 3.9kΩ and R2 = 10kΩ give 2.5V × (1 + 3.9/10) = 3.48V. Below that it draws under 1µA; above it, it sinks the excess (up to 100mA). Set the threshold 4-5% above the LDO setpoint. If it is narrower than the LDO's ±2% plus the TL431 side's ±2%, the TL431 can sink the LDO's whole output continuously and overheat. For injection above 100mA, drive a PNP from the TL431 so the PNP takes the heat.

3. Make the output stage push-pull. The error amplifier drives an NPN (source) and a PNP (sink). DDR VTT regulators and the LT1118 (source 800mA, sink 400mA) take this form.

In every case, the energy of the sunk current becomes heat: 0.33W for 100mA at 3.3V. Only a synchronous switching regulator can return it to the input instead. An LDO's active discharge (a roughly 100Ω FET that pulls the output to GND only while EN is low) acts as a 100Ω load under injection and settles the rail at 4.4 / (1 + 220/100) ≈ 1.4V. That is below many MCUs' brown-out thresholds, but not 0V.

Why an ordinary LDO is not push-pull

An ordinary LDO's output stage is a single pass element. A supply load draws current toward GND, so there is no reason for a low-side transistor. That differs from an op-amp, which swings a signal above and below a midpoint.

Even as push-pull, loss while sourcing equals an ordinary LDO's because the low side is off. The costs lie elsewhere. 1. Crossover. Tying the two bases leaves a ±0.6V dead zone (class B); biasing it (class AB) raises no-load idle current. 2. Thermal design. The sink side turns all of V_out × I_sink into heat. 3. Dropout. An emitter-follower build needs V_BE plus margin, over 1V, so it is no longer low-dropout.

Also, being able to sink is not always good. If the regulator could sink in the Figure 1 situation, the rail would stay at 3.3V but the 5V-side output would keep driving (5 − 0.6 − 3.3) / R_s (5mA at 220Ω, as much as the driver can give if wired directly). The overvoltage problem just becomes an overcurrent and heating problem.

That is why push-pull LDOs are limited to loads that truly draw current both ways (DDR VTT, midpoint voltages), such as the TPS51200 and LT1118. Stop accidental inflow at its entry point: series resistance, I_off, or level translation.

A load that truly needs sinking: DDR VTT termination

The classic sink-capable regulator is the DDR termination voltage VTT, and ICs for it say so in the title (TI's TPS51200 is a "Sink/Source DDR Termination Regulator").

In SSTL, each data line is pulled to VTT = VDDQ / 2 through a termination resistor R_T (around 50Ω; DRAM's on-die termination for DDR3 and later). For DDR3, VDDQ = 1.5V and VTT = 0.75V. A line driven high (1.5V) sends 15mA into VTT; a line driven low (0V) draws the same 15mA out of VTT. The VTT regulator sinks for high lines and sources for low lines.

With 64 data lines plus strobes and addresses, all high is over 1A flowing in, all low over 1A flowing out. Real data is close to random, so the average stays near zero while the instantaneous value swings both ways. An ordinary LDO lets VTT rise when many lines are high, leaving the 0.75V ± tens of mV spec.

A capacitor sinks only for a moment

A capacitor obeys I = C·dV/dt and takes current only while its voltage is rising. It sinks pulses but not DC.

Take the Figure 1 example with a 10µF output capacitor and injection from 5V through 220Ω. The inflow starts at 5mA, and the charge needed to lift the rail to 4.4V is 10µF × 1.1V = 11µC, about 2ms (time constant 220Ω × 10µF = 2.2ms). The capacitor buys only a few ms, which does nothing when the 5V side stays high. Lasting one second would take 5mA × 1s / 1.1V ≈ 4.5mF.

For short pulses the capacitor alone is enough. For VTT too, currents changing at MHz rates go to the capacitors, and the regulator handles the average and the slow components. A capacitor buys time; it is not a destination for current. For DC inflow you need a bleed resistor, a series resistor, or a regulator that can sink.

Where this bites on real boards

• Powering off with a USB-serial adapter still connected. The adapter's TX feeds the MCU rail through the RX protection diode, leaving it at 2-3V so the MCU seems not to restart. Add 1kΩ or more in series on the adapter side, or put an I_off buffer in between.
• Two boards connected, one powered first. The powered side's outputs lift the unpowered side's rail. Put a bus switch or level translator at the boundary.
• I2C pulled up to the higher supply. SDA/SCL pulled up to 5V and connected to a 3.3V device inject (5 − 0.6 − 3.3) / 4.7kΩ ≈ 230µA per line while high with a 4.7kΩ pull-up, more than a sleeping load.
• Stopping a motor or solenoid with an H-bridge. Regenerative braking returns current to the supply, and a power-save buck or small capacitor lets the voltage jump. Absorb it with bulk capacitance, a brake resistor, or a TVS.
• Two regulators with different setpoints on one rail. The higher one takes the whole load and the lower one stays closed, with no load sharing.
• How to check. Power the board off, connect only the interfaces, and measure the rail. Anything other than 0V means current is coming in. While running, put the load in its lightest state (sleep), hold the boundary signal high, and see whether the rail rises.
• What to look for in datasheets. For an LDO: "reverse current" and "active discharge". For a synchronous converter: "forced PWM / FCCM" and "negative current limit". For VTT: "source/sink current".