Electric Calculator for hardware engineers
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Synchronous buck converter: efficiency, ripple and waveforms

A first-pass calculation for a synchronous buck converter. It works out the inductor current ripple and the capacitive part of the output ripple, and plots both waveforms.

V
V
A
Hz
H
F

SI prefixes accepted (4k7 / 1M / 10m / 220). Upper-case M = mega, lower-case m = milli

ΔIL (p-p)
2.6515A
IL peak3.3258 A
ΔVout (p-p)30.129 mV
Efficiency (estimate)99.741 %
Advanced — Rds(on) HS, Rds(on) LS
Ω
Ω
History
Press Enter in any field to keep a snapshot here.

Formula

Formulas (ideal approximation):
Duty D = Vout / Vin
Inductor current ripple ΔIL(pp) = (Vin - Vout) × D / (L × fsw)
Output ripple (C only) ΔVout(pp) ≈ ΔIL / (8 × fsw × Cout)
FET conduction loss (resistive only) P = Rds(on) × (1/T)∫ i(t)^2 dt

Design notes

Waveforms: one switching period of the inductor current iL and of the output ripple vout-ripple from the capacitor alone (ESR ignored).

iL(t) [A]
vout ripple(t) [mV] (capacitor only)

Note: the efficiency here counts only the conduction loss in the Rds(on) of the high-side and low-side FETs. Inductor DCR, output capacitor ESR, switching loss, dead-time loss and gate drive loss are all left out.

When you need this

For selecting the inductor and output capacitor of a synchronous buck converter. It reports ripple current, peak current, output ripple voltage and an efficiency estimate together, so you can check whether the datasheet's recommended values hold for your operating point.

Choosing the inductor

Inductance is set by the ripple current ΔIL. Convention is to land it at 20–40% of the rated output current.

Smaller ripple lowers output ripple voltage and lets you use a smaller capacitor, but the inductor grows and costs more. Larger ripple raises peak current, eroding saturation margin and increasing core loss.

The number to check when selecting an inductor is IL peak. Confirm the datasheet saturation current Isat comfortably exceeds it. Once saturated, inductance collapses and current runs away. Transients push the peak higher still, so allow 1.2–1.5 times margin on Isat.

Output capacitor

Output ripple ΔVout is the sum of a capacitive term and an ESR term. This calculator reports the capacitive term.

Ceramics have low ESR so the capacitive term dominates — but watch that DC bias derating substantially reduces effective capacitance. A 25V-rated 10µF part at 12V may retain only 4–5µF. Calculate with the effective value, not the nameplate.

Reading the efficiency figure

The efficiency here accounts only for MOSFET conduction loss (I²R through Rds(on)). Real converters also lose to switching, gate drive, inductor copper and core loss, and controller consumption.

Expect the measured efficiency to be 3–8 points below this figure, with the gap widening at high switching frequency or large input-to-output ratio. For accurate numbers, use the vendor's simulator or measure.

What layout decides

  • Input capacitor placement matters most. Minimise the loop from the high-side MOSFET drain to ground (the hot loop). A large loop produces ringing and spikes, causing EMI and device stress.
  • Keep the switch node small. It swings fast and high, so a large copper area radiates. It also carries heat, so do not shrink it to nothing either.
  • Route feedback away from the switch node. Do not run the most sensitive net past the noisiest one. Shield it with ground or move it to another layer.
  • Bring grounds to one point. Tie the input capacitor, output capacitor and IC ground pin together by the shortest path.

Frequently asked questions

What percentage should ripple current be?
20–40% is the usual guideline. Start near 30% and adjust against inductor size and output ripple. Too little means a bulky inductor; too much raises peak current and losses. If light-load efficiency matters, lean towards higher inductance.
The efficiency does not match my bench measurement.
This estimate covers MOSFET conduction loss only — no switching loss, gate drive, inductor loss or controller consumption. Real hardware typically comes in 3–8 points lower. Use it for trends, not absolute numbers.
Are ceramic output capacitors enough?
For most ICs, yes. But loop stability sometimes depends on capacitor ESR, and a few controllers oscillate with ceramics alone. Follow the datasheet's recommended configuration. Also, because of DC bias derating, fitting about twice the calculated capacitance is a safe approach.
Can I calculate the load transient response?
Not here — this covers steady-state ripple. The dip on a load step is set by loop bandwidth and output capacitance. A rough estimate is ΔV ≈ ΔI /(2π × fc × Cout), where fc is the loop crossover frequency.

Standards and references

  • IEC 61204-3 — DC power supply performance and EMC.
  • CISPR 32 — Radiated and conducted emission limits relevant to switching supplies.

Last updated: 2026-08-29