Do not put an LED on a pin that is read at boot (a strap pin)

What a strap pin is: voltage read only at reset release

Many ICs sample the voltage on certain pins exactly once, at the moment reset is released (or configuration starts), and decide their later behavior from it. These are strap pins. What happens to the pin after sampling depends on the device.

On the ESP32, GPIO0, GPIO2, GPIO12 (shared with JTAG MTDI) and GPIO15 (shared with MTDO) are read as boot-mode pins only just after startup, and afterward are free GPIOs. It is easy to think they no longer matter once boot ends, but the voltage is decided at the moment of power-up itself. The STM32 BOOT0 (a dedicated pin on many parts) and the configuration-mode pins of many FPGAs (M[2:0] on Xilinx 7 series, MSEL on Intel/Altera and so on) cannot be reused as GPIO, but the behavior is still set by the voltage right after startup.

Ethernet PHY address and mode pins fall in between. The PHY address and operating mode are set by straps read from an external resistor at reset release, and many parts reuse the same pin as an LED driver (LINK/ACT) afterward. The strap and the LED output share one pin, so this is where accidents are most likely in this article.

Example: ESP32 GPIO12 and the flash voltage

The best-known example is ESP32 GPIO12 (the VDD_SDIO strap, shared with MTDI). GPIO12 has an internal pull-down and by default reads L, which sets the internal flash voltage regulator to 3.3V. If it is H at reset release, the regulator selects 1.8V. With a 3.3V flash on the board, 1.8V cannot be read correctly and the result is a board that will not boot, or flash contents that look garbled.

This is a plain H/L decision on one digital input, so an LED that seems unrelated can break it just by being connected to the pin.

Why an LED plus a resistor makes an "in-between" voltage

The internal pull resistor of an MCU is usually about 30 to 50kΩ (made weak on purpose to save current). Add an LED and a resistor and the strap node becomes a divider of the internal pull and the external LED + resistor. An LED is nonlinear, with a forward voltage that changes with current, but treating it as roughly constant shows why accidents happen.

Take an internal pull-down R_pd = 45kΩ, with the external path from 3.3V through R_ext and an LED (forward voltage V_F ≈ 1.8V) into the node: the common wiring of an LED that lights when the pin is low. The node voltage is V = R_pd(V_DD − V_F) / (R_pd + R_ext) and the LED current is I = V / R_pd.

The current is capped by R_pd (45kΩ) anyway, so even with R_ext down to 1kΩ the LED carries only tens of µA. The LED does not visibly light, yet the node voltage moves into the 1V range. "The LED is dim, so it is fine" does not hold on a strap pin. Also, the LED's forward voltage falls at low current, so the real V_F at tens of µA is below 1.8V and the node voltage is higher than this estimate. It is not a conservative estimate.

Choosing values: check the node stays inside the VIH/VIL bands

Whether the node reads H or L is set by the pin's VIH (the lowest voltage read as High) and VIL (the highest read as Low). With the general CMOS rule of thumb VIH ≈ 0.7×V_DD and VIL ≈ 0.3×V_DD, a 3.3V system has VIH = 2.31V and VIL = 0.99V. On real hardware, check the VIH/VIL in that pin's datasheet. Some parts use stricter thresholds, such as a Schmitt trigger with hysteresis.

Here is a table for R_ext against the 45kΩ internal pull (V_DD = 3.3V, LED V_F ≈ 1.8V, simplified).

As the table shows, the resistances that make an LED usefully bright (hundreds of Ω to a few kΩ) almost surely land in the undefined band. A larger resistor leaves the LED dark, so the two goals conflict. The conclusion is not to put an LED directly on a strap pin; if you must, insert one buffer stage so the strap voltage is unaffected.

Another thing to check is whether the node voltage has settled by reset release. A capacitor on the strap net delays settling by the RC time constant with the internal pull. For R_pd = 45kΩ, τ = R×C is 45µs for 1nF (5τ = 0.225ms), 4.5ms for 100nF (5τ = 22.5ms) and 45ms for 1µF (5τ = 225ms). Reset ICs often delay tens to hundreds of ms, so a few hundred pF to a few nF is fine, but a few hundred nF to 1µF added "just in case" brings 5τ close to reset release, and lot, temperature and supply-ramp variation can make the pin be read before it settles.

Inputs of other ICs also push current in

The LED is not the only cause. If a level-shifter or logic-gate input hangs on the same strap net, current flows into and out of the net through that IC's internal pull-up or pull-down and its input protection (ESD) diode. It is dangerous when that IC is on a different supply and powers up in a different order.

For example, if the buffer IC's supply has not risen yet while the strap-side supply (or the pull-up behind it) reaches 3.3V first, current flows through the buffer's input protection diode into its supply rail, still near 0V. Current with nowhere to go raises the rail, the same structure as the protection-diode injection in An LDO cannot sink current. Seen from the strap net, the divider of internal pull and external load gains one more path that current can enter or leave.

Ethernet PHY: the strap and the LED driver are the same pin

Many Ethernet PHYs set the PHY address and operating mode with external resistors at reset release. Many datasheets tell you to make that resistance well below the internal pull (the specified value) so the external resistor's intent surely wins. So far this is the same divider of internal pull and external resistor.

What is specific to PHYs is that many parts reuse the pin after reset release as the output of an LED driver for LINK/ACT. The resistor used for the strap doubles as the LED's current-limiting resistor. This is intended, and fine if designed correctly. The trouble comes when the resistance is chosen only for address setting and the LED does not light, or when it is lowered too far to brighten the LED and the PHY address ends up different from intended: caught from both sides.

Another point is the active H/L direction. Just as connecting the strap resistor to VDD or GND changes the address bit, the LED direction (whether the PHY sinks or sources) must be decided by reading both the strap table and the LED drive description in the datasheet. Reading only one gives a correct address with an LED that stays dark, or the reverse.

Seeing the instant at startup

The voltage that matters means something only at the instant of reset release. A meter on the steady state, after firmware drives the pin as a GPIO, no longer shows the voltage just after startup. Trigger an oscilloscope on the rising edge of the reset signal (EN, CHIP_PU and so on) and watch the strap net at the same time; this is the only way to confirm on real hardware.

As Figure 3 shows, during reset the node settles at some voltage set by the divider of the internal pull and the external LED, and at release that voltage is latched once. If it lies in the undefined band, whether it reads H or L can change with unit variation, temperature and small supply differences.

In a table: where in the VIH/VIL bands does it land

Figure 4 lines up the four cases from the earlier table against the voltage bands. Only the dim-LED condition at 47kΩ reads L with certainty, and staying out of the undefined band is the basic criterion for choosing values.

設計レビューのチェック手順

1. List the strap pins. Search the datasheets for "strap," "boot mode" and "configuration mode," and write down each pin and whether it returns to GPIO after reset release.
2. Find every part on that net. Pick up the LEDs, pull resistors, wiring to connectors and other ICs' input pins (including internal pulls and protection diodes) from the schematic.
3. Check the internal pull value in the datasheet. If it is given as a range, calculate for the worst case (no pull, or the weakest value).
4. Calculate the node voltage with V = R_pull(V_DD − V_F) / (R_pull + R_ext) and compare it with that pin's own VIH/VIL (not the generic 0.7/0.3×V_DD). If the LED has several colors, use the one with the lowest V_F (often red).
5. If there is an external capacitor, calculate τ = R_pull × C and check that 5τ is well below the reset IC's delay.
6. For pins shared by strap and LED, such as on a PHY, read both the address table and the LED drive description and check that the resistance satisfies both. If it cannot, move the LED to another pin.
7. On real hardware, trigger on the rising edge of reset and check the strap net on a scope, then vary the supply voltage and temperature to confirm it never touches the undefined band.

What catches people on real boards

"I added one debug LED and it stopped booting" is typical of a status LED on a boot-mode pin such as GPIO0, GPIO2 or GPIO12: normal boot and download mode swap, or the flash voltage no longer matches. Boards that boot on some units and not others come from unit-to-unit and temperature variation in the internal pull, the LED's V_F and VIH/VIL; a design right at the edge of the undefined band flips either way with production variation.

If a symptom appears after changing the supply voltage (3.3V to 2.5V, for example), V_DD falling lowers the absolute VIH/VIL while the LED's V_F stays nearly constant, so the relation to the divider point changes. With several V_DD options, recalculate at the lowest one. A noise-suppression capacitor of a few hundred pF is usually harmless, but adding EMI or ESD parts casually can stretch the RC time constant until it misses reset release.