Via inductance is what dulls your decoupling

A capacitor turns into an inductor above some frequency

Every real capacitor carries a series inductance, ESL, from its electrodes and terminations. Above the series resonance of capacitance C and ESL, f = 1 / (2π√(L·C)), impedance rises in proportion to frequency and the part stops behaving as a capacitor.

ESL for a 1608 (0603) MLCC runs 0.5–0.7nH, and for a 1005 (0402), about 0.4–0.5nH. For 0.1uF with 0.5nH of ESL, resonance sits at 22MHz — above that it is a 0.5nH inductor, not a capacitor. Its impedance at 100MHz works out to 2π x 100M x 0.5n = 0.31Ω.

That is the capacitor in isolation. On a real board, the path from the capacitor's pad to the IC's power pin adds trace and via on top of it.

Inductance added by the trace and the via

Via inductance is approximated by L ≈ 5.08·h·[ln(4h/d) + 1] for a via of length h and hole diameter d (h and d in inches, L in nH). A 0.3mm-diameter via through a 1.6mm board comes to about 1.2nH. But current only flows through the section from the capacitor's pad to the reference plane, so if that plane sits on layer 2 (0.2mm below the top layer), the effective via length is short and the contribution is only about 0.1–0.2nH.

The trace is the bigger problem. A short lead-out from pad to via, on a thin trace over a plane, carries roughly 0.5–1nH/mm. Apply a common layout rule of "keep the via 2mm from the pad" and that alone adds 1–2nH — 2 to 4 times the capacitor's own ESL.

Add it all up and a 0.1uF 1608 placed in an ordinary way ends up with 1.5–3nH total. The resonant frequency drops from 22MHz (at 0.5nH) down to 11MHz at 2nH, and the impedance at 100MHz rises to 1.3Ω.

Layout choices that recover 1nH

Improving decoupling means cutting inductance, not adding capacitance. Ranked by impact:

Put the via right against the pad. Shrinking the trace between pad and via toward zero has the biggest effect. Via-in-pad is ideal if you can do it, though it needs resin fill or a small-diameter via to stop solder from wicking into the hole. Even just tucking the via against the side of the pad, rather than 2mm away, saves more than 1nH.

Bring both the power-side and GND-side vias in close. Current flows in a loop. A distant GND via cancels out any benefit from tightening up the power side.

Use two vias. A naive calculation says parallel vias halve the inductance, but mutual inductance between adjacent vias keeps the cancellation from being complete — the real reduction is more like 60–70%. Still worth roughly 0.5nH.

Put the reference plane on a layer close to the top. On a 4-layer board with layer 2 as GND, the via from a top-layer capacitor down to GND is only 0.2mm long. This is why top-layer parts so often sit right above a GND plane.

Place the capacitor directly under the IC's pins, on the back side. When there is no room on the top layer, mounting the capacitor on the back directly beneath the IC and connecting through a via leaves only the through-board via (1.6mm) in the path — shorter than a 5mm run on the top layer.

The old rule of "parallel a 0.1uF with a 0.01uF for wide bandwidth" actually creates an anti-resonance (an impedance peak) between the two differently-tuned resonances. Paralleling several capacitors of the same value and size instead lowers impedance without creating that peak.

Plane-to-plane capacitance, and the frequency where capacitors stop mattering

Placing a power plane next to a GND plane creates distributed capacitance between them. In FR-4 (εr ≈ 4.3), a 0.1mm gap gives about 38pF/cm², and 0.2mm gives 19pF/cm². A 10cm x 10cm board at 0.1mm spacing works out to 3.8nF — small as a number, but this "capacitor" has no via and no trace, so its inductance is essentially zero.

Above a few hundred MHz, discrete capacitors stop contributing because of their inductance, and the job passes to plane capacitance and the capacitors inside the package and the die. The role of the decoupling capacitor is to cover the band beneath that — roughly a few MHz up to the low hundreds of MHz.

That is why "many 0.1uF capacitors, each placed as tightly as possible" is the standard approach. Parallel ten 0.1uF capacitors and each 2nH of inductance becomes an effective 0.2nH, bringing the 100MHz impedance down to 0.13Ω. Ten 0.1uF capacitors beat a single 1uF capacitor at high frequency.

Checking it on real hardware

The reliable way to judge a layout is to measure the power-to-GND impedance with a network analyzer rather than looking at noise on the power pin directly. A two-port shunt measurement swept from 100kHz to 1GHz reveals the resonance and anti-resonance peaks and valleys, showing which capacitor is doing the work at which frequency.

Without that equipment, an oscilloscope reading ripple right at the power pin, using a ground spring (the probe's short GND tip), is the next best thing. Measure with a GND lead wire a few cm long instead, and that lead's own inductance rides straight into the reading, making the noise look worse than it is — at which point you can no longer tell whether you're measuring the capacitor layout or the probe's own layout.