Via inductance is what dulls your decoupling

A capacitor turns into an inductor above some frequency

Every real capacitor has a series inductance, ESL, from its electrodes and terminations. Above the series resonance of C and ESL, f = 1 / (2π√(L·C)), impedance rises in proportion to frequency and the part stops behaving as a capacitor. ESL is 0.5–0.7nH for a 1608 (0603) MLCC and about 0.4–0.5nH for a 1005 (0402).

For 0.1uF with 0.5nH of ESL, resonance sits at 22MHz and above that it is a 0.5nH inductor. Its impedance at 100MHz is 2π × 100M × 0.5n = 0.31Ω. On a real board, the trace and via from the pad to the IC's power pin add to this.

Inductance added by the trace and the via

Via inductance is approximated by L ≈ 5.08·h·[ln(4h/d) + 1] for length h and hole diameter d (inches; L in nH). A 0.3mm via through a 1.6mm board is about 1.2nH, but current only flows from the pad to the reference plane. With the plane on layer 2 (0.2mm below the top), the effective length is short and the contribution is about 0.1–0.2nH.

The trace is the bigger problem. A short lead-out from pad to via on a thin trace over a plane carries roughly 0.5–1nH/mm. Keep the via 2mm from the pad and that adds 1–2nH, 2 to 4 times the ESL. An ordinary 0.1uF 1608 totals 1.5–3nH: resonance falls to 11MHz at 2nH and the impedance at 100MHz rises to 1.3Ω.

Layout choices that recover 1nH

Improving decoupling means cutting inductance, not adding capacitance. Ranked by impact:

Put the via right against the pad. Shrinking the trace between pad and via toward zero helps most. Via-in-pad needs resin fill or a small via. Tucking the via beside the pad saves over 1nH versus 2mm away.

Bring both power-side and GND-side vias in close. Current flows in a loop, so a distant GND via defeats the rest.

Use two vias. Mutual inductance keeps the reduction at 60–70%, not half. In the table, 2.0nH becomes 1.3nH.

Put the reference plane close to the top layer. With layer 2 as GND on a 4-layer board, the via is only 0.2mm long.

Place the capacitor under the IC, on the back side. With no room on top, only the board-thickness via (1.6mm) is in the path, shorter than a 5mm run on the top layer.

The old rule of paralleling a 0.1uF with a 0.01uF for wide bandwidth creates an anti-resonance (an impedance peak) between the two resonances. Paralleling several capacitors of the same value and size lowers impedance without that peak.

Plane-to-plane capacitance, and the frequency where capacitors stop mattering

A power plane next to a GND plane forms distributed capacitance. In FR-4 (εr ≈ 4.3), a 0.1mm gap gives about 38pF/cm² and 0.2mm gives 19pF/cm². 10cm × 10cm at 0.1mm is 3.8nF, small, but with no via and no trace, its inductance is essentially zero.

Above a few hundred MHz, plane capacitance and the capacitors inside the package and die take over; decoupling capacitors cover a few MHz up to the low hundreds of MHz.

Hence many 0.1uF capacitors, each placed tightly. Ten in parallel turn each 2nH into an effective 0.2nH, bringing 100MHz impedance down to 0.13Ω. Ten 0.1uF beat a single 1uF at high frequency.

Checking it on real hardware

The reliable check is to measure power-to-GND impedance with a network analyzer. A two-port shunt sweep from 100kHz to 1GHz shows the resonances, anti-resonances and which capacitor works where.

Without one, read ripple at the power pin with a ground spring (the probe's short GND tip). A GND lead a few cm long adds its own inductance, so you cannot tell the capacitor layout from the probe's.