Buck duty cycle is not set by Vout/Vin alone: minimum on-time and pulse skipping

D = Vout/Vin is the ideal value

Textbooks give the buck converter duty cycle as D = Vout/Vin. That is the answer for an idealized model in which the switch and inductor have no resistance and switching is instantaneous. A real controller runs on feedback and adjusts the duty cycle every cycle, so the deviation from this formula is corrected automatically. The problem is not the deviation itself but a case where the required on-time or off-time passes the controller's physical limit and cannot be corrected.

We first put numbers on the deviation (the flip side of the losses in where a synchronous buck converter loses power), then look at what happens at the minimum on-time wall and the minimum off-time (maximum duty) wall.

The real duty cycle shifts with Rds(on), DCR and dead time

In the averaged model of a synchronous buck, let the load current be I, the high-side Rds(on) R_hs, the low-side Rds(on) R_ls and the inductor DCR R_L. From volt-second balance, the duty cycle actually needed is:

D_actual = (Vout + I·(R_L + R_ls)) ÷ (Vin − I·R_hs + I·R_ls)

With Vin = 12V, Vout = 3.3V, I = 3A, R_hs = 30mΩ, R_ls = 15mΩ and R_L (DCR) = 20mΩ, the ideal D₀ = 3.3 ÷ 12 = 0.275 becomes D_actual ≈ 0.2848. The difference is +0.98 points (+3.6% of the ideal).

Dead time shifts it the same way. While both the high-side and low-side switches are off, the current flows through the low-side body diode with a forward drop V_F ≈ 0.5-0.6V. Dead time occurs twice per cycle, so the effect on the output voltage is about ΔV ≈ 2·fsw·t_dead·V_F. For fsw = 2MHz, t_dead = 10ns and V_F = 0.55V that is about 22mV, and 44mV for t_dead = 20ns.

Adding these, switching at D₀ = 0.275 would give a Vout of about 3.16V (about 4.2% below target). The feedback loop senses this and raises D until Vout settles at 3.3V, so the actual duty cycle is always a little larger than the ideal Vout/Vin.

The minimum on-time wall: 24V to 1.0V at 2MHz

The on-time needed at the ideal duty cycle is ton = D0 ÷ fsw = (Vout/Vin) ÷ fsw. For Vin = 24V, Vout = 1.0V and fsw = 2MHz (500ns period), ton = (1.0 ÷ 24) ÷ 2MHz ≈ 20.8ns. The real ton is slightly longer, but it makes little difference.

Synchronous buck controller ICs have a minimum on-time limit from gate-driver propagation delay, slope compensation, current-sense blanking and so on. Typical values are 50-100ns in the Electrical Characteristics table (it varies by part). 20.8ns is less than half the low end of that range, so making 24V to 1.0V at 2MHz with a single-stage buck is out of reach for most parts from the start.

The table below shows the required on-time for different combinations of Vin, Vout and fsw. Taking a minimum on-time of 50ns, the combinations below it (in bold) will not run properly as a single stage.

What happens below the wall

When the required ton is below the minimum on-time, the controller has two options.

• (1) Clamp ton at the minimum. Since ton cannot shrink, each pulse delivers more energy than needed. In Figure 2, at Vin = 20V the required ton is 25ns, but clamped at the 50ns minimum each pulse carries twice the energy. With fsw unchanged, the average duty cycle would be 0.1 (10%) instead of 0.05 (5%), and the output rises toward twice the target (1.0V to 2.0V).
• (2) Drop pulses (pulse skipping, frequency foldback). Keep ton at 50ns and switch only once every two cycles, and the average duty cycle returns to 0.1 ÷ 2 = 0.05, so the output settles at 1.0V. The effective switching frequency, though, halves from 2MHz to 1MHz. If a heavier load needs more ton, the skip interval shortens, and a lighter load skips more, so the effective frequency moves with the load.

To the output filter, the skip period (every two cycles in this example) is a new, lower frequency component (fsw/2 = 1MHz). The filter corner is set relative to fsw, so components below fsw are attenuated less than designed and the ripple comes out larger than calculated (subharmonic ripple). The EMI spectrum also spreads below fsw instead of being a single line, so a filter designed only for fsw and its harmonics may fall short. If the effective frequency falls to the audible band (up to 20kHz), coil whine appears.

The other wall: maximum duty and dropout

The same limit exists where the duty cycle approaches 1. Most synchronous bucks recharge the bootstrap capacitor that drives the high-side MOSFET gate by periodically turning the low side on, so the high side cannot stay on 100% of the time. The minimum on-time reserved for the low side (the minimum off-time) sets the maximum duty D_max = 1 − t_off(min) ÷ T (parts with a dedicated 100%-duty circuit are an exception).

For fsw = 2MHz (500ns period) and a typical minimum off-time of 80ns, D_max = 1 − 80 ÷ 500 = 0.84. To hold Vout = 3.3V the minimum Vin is 3.3 ÷ 0.84 ≈ 3.93V.

In a 5V to 3.3V supply this is not on your mind (D = 0.66, toff = 170ns). It matters where input and output are close, such as making 3.3V from a lithium-ion cell that starts at 4.2V. The battery voltage falls as it discharges, so the situation changes as in the table below.

Once the battery discharges to 3.7V, the required toff shrinks to 54ns, but the controller cannot go below 80ns. The minimum on-time side had pulse skipping as a way out, but here the duty cycle is already stuck at its limit, so there is nothing to catch up with. The duty cycle stays at D_max = 0.84 and Vout falls in proportion to Vin, Vout = D_max·Vin: literal dropout. At 3.7V, Vout ≈ 0.84 × 3.7 ≈ 3.11V (about 5.8% below target), and at 3.5V about 2.94V (about 10.9% below).

The forbidden region on the Vin-fsw plane

Fixing Vout and plotting the minimum on-time limit on the Vin-fsw plane shows at a glance where a single-stage buck can work. Solving ton = (Vout/Vin) ÷ fsw ≥ ton(min) for fsw gives fsw ≤ Vout ÷ (Vin·ton(min)). The region that does not satisfy it (above the boundary curve) is the forbidden region.

The figure below uses Vout = 1.0V and draws the boundary for a 50ns minimum on-time (dark fill) and for a faster 30ns part (dotted, for reference). The point for 24V to 1.0V at 2MHz (cross) is inside the forbidden side of both boundaries, so a faster part alone does not fix it. For 12V to 1.0V at 2MHz (circle), the 50ns part is in the forbidden region, but the 30ns part can run.

Choosing: lower fsw, two stages, or a shorter minimum on-time

When you hit the minimum on-time wall, you have these three options.

In practice you combine the three. As a rule of thumb, an extreme step-down ratio (24V to 1V class) is realistically a two-stage design, while a moderate ratio (12V to 1V class) often stays single-stage with a shorter minimum on-time part and a somewhat lower frequency. Start by comparing ton = (Vout/Vin) ÷ fsw with the minimum on-time in the datasheet of the part you plan to use.

Where it goes wrong on real boards

The efficiency curve worsens only at high Vin and light load. Once pulse skipping starts, each pulse carries too much energy and the transfer efficiency drops against switching loss. Measure efficiency at each Vin; a deeper dip only at high Vin is the sign.

Ripple is much larger than calculated, and the waveform differs every few cycles. The output filter is designed for ripple at fsw, so when pulse skipping moves the ripple below fsw it no longer matches the calculation. A peak at something other than a multiple of fsw in an EMI measurement is a sign of the same behavior, with the effective frequency moving with load and Vin.

On a battery-powered device, the output rail may sag slowly as the charge falls. It can be maximum-duty dropout sagging the rail before the voltage monitor threshold is reached. Log the battery voltage and the output rail together and check that the D_max·Vin calculation matches the measurement.

If the switch-node ton (or toff) looks stuck at one width as you vary Vin or Vout, that is direct evidence it is clamped at the minimum on-time (or off-time). Compare with Minimum On-Time, Minimum Off-Time, Maximum Duty Cycle, and whether 100% Duty Cycle Operation exists in the datasheet. PFM/Skip-Mode Frequency indicates the effective skip frequency.