Where the loss actually goes in a synchronous buck converter
In a buck converter running at 92% efficiency, tracing where the remaining 8% turns into heat sets your priorities. Lower the MOSFET's RDS(on) alone, and switching loss and the inductor still account for 70% of the total.
The conditions for this calculation
Take a synchronous buck converter: 12V in, 3.3V out, 3A output current, 500kHz switching frequency, 4.7µH inductor. Duty cycle D = 3.3 ÷ 12 = 0.275. High-side MOSFET RDS(on) = 20mΩ, low-side 10mΩ, each with gate charge Qg = 10nC, 5V gate drive, a 20ns switching transition, 20ns dead time on each edge, and a body-diode forward voltage of 0.8V. Inductor DCR = 20mΩ.
The ripple current is ΔI = (Vin − Vout) × D ÷ (f × L) = 8.7 × 0.275 ÷ (500k × 4.7µ) ≈ 1.0A peak-to-peak, or 34% of the output current.
Working through each loss term
Conduction loss is I² × RDS(on) × D = 3² × 0.02 × 0.275 = 50mW on the high side and 3² × 0.01 × 0.725 = 65mW on the low side. At a low duty cycle the low side is on longer, so cutting its RDS(on) has more leverage. Switching loss, from voltage and current overlapping during the transitions, is approximately 0.5 × Vin × Iout × (tr + tf) × f = 0.5 × 12 × 3 × 40n × 500k = 360mW, the largest term here. The low side switches at zero voltage and has almost none.
Gate drive for both switches is Qg × Vdrv × f = 10n × 5 × 500k × 2 = 50mW. Dead time, while the body diode carries current, is 0.8 × 3 × 20n × 2 × 500k = 48mW, and inductor copper loss is I² × DCR = 9 × 0.02 = 180mW. Core loss comes from the vendor's tool, roughly 50 to 100mW for a ferrite core under these conditions. Output capacitor ESR loss (0.29A RMS ripple, 0.4 to 4mW) and controller current (20 to 50mW) are small.
| Item | Loss | Share | Main driving parameter |
|---|---|---|---|
| High-side switching | 360mW | 42% | tr + tf, f, Vin |
| Inductor copper loss | 180mW | 21% | DCR |
| Inductor core loss | 75mW | 9% | ΔI, f, core material |
| Low-side conduction | 65mW | 8% | RDS(on), 1 − D |
| High-side conduction | 50mW | 6% | RDS(on), D |
| Gate drive | 50mW | 6% | Qg, f |
| Dead time | 48mW | 6% | tdead, Vf |
| Controller and other | 30mW | 3% | — |
| Total | About 860mW | 100% | Efficiency ≈ 92% |
That is 0.86W of loss against 9.9W of output, or 92% efficiency. Conduction loss adds up to only 115mW, 13% of the total, while switching loss and the inductor take 70%. To gain efficiency, look first at the MOSFET's transition time and the inductor's DCR.
What happens when you raise the frequency
Raising frequency from 500kHz to 2MHz reduces the inductance needed for the same ripple to about one quarter, 1.2µH. With transition times, gate charge and dead time held constant, switching loss rises from 360mW to 1.44W, gate-drive loss from 50mW to 200mW, and dead-time loss from 48mW to 192mW. Holding other losses constant gives approximately 0.86 + 3 × (0.36 + 0.05 + 0.048) = 2.23W, for 9.9 / (9.9 + 2.23) ≈ 81.6% efficiency. A different inductor also changes DCR and core loss, so recalculate with the selected parts.
2MHz makes sense when size is the top priority, or when Vin is low enough that switching loss, which is proportional to Vin, stays small (under half at 5V compared with 12V). Switching at a high input voltage costs a lot, so generating 3.3V from 48V can be more efficient as two stages, 48V→12V then 12V→3.3V.
Why efficiency falls off at light load
Drop the output current from 3A to 0.3A and conduction and copper loss fall to 1/100 (current squared), but gate drive loss, controller quiescent current, part of the dead-time loss and core loss stay regardless of current. In the example that fixed share is around 150mW, so efficiency is below 85% at 1W of output.
In synchronous rectification, once the inductor current goes below zero, current flows back out through the low side. Most controllers detect this at light load and either turn the low side off (diode emulation) or switch into a PFM mode. Under PFM the fixed losses scale down with the lower switching frequency, so efficiency holds even at tens of mA. If standby current is higher than predicted, the converter is often not entering its light-load mode, so check the datasheet for the current where it does.
Losses that come down to layout
Some losses never show up in the calculation. The loop of the input capacitor, high side and low side (the hot loop) sees current jump from 0 to 3A on every switching edge. Too much parasitic inductance puts a spike on the switch node, and absorbing it with a snubber or extra gate resistance adds loss.
Minimize the area of the hot loop. Place the input capacitor right next to the MOSFETs, keep the loop closed within a single layer, and keep the switch-node trace short and small.
The synchronous buck converter calculator runs this article's loss calculation from your input values.
Frequently asked questions
Should I just pick the MOSFET with the lowest RDS(on)?
My measured efficiency is worse than the calculation.
How much inductor ripple current should I design for?
How much better is this than a non-synchronous (diode) buck converter?
Standards and references
- TI SLVA477, Basic Calculation of a Buck Converter's Power Stage — Basic calculation of duty cycle, ripple current, and component values
- MOSFET vendors' application notes (switching loss calculation) — Estimating loss from Qgd, transition time, and driver current
- Inductor vendors' loss calculation tools — Calculating DCR, AC resistance, and core loss