Where the loss actually goes in a synchronous buck converter

The conditions for this calculation

Take a synchronous buck converter: 12V in, 3.3V out, 3A output current, 500kHz switching frequency, 4.7µH inductor. Duty cycle D = 3.3 ÷ 12 = 0.275. High-side MOSFET RDS(on) = 20mΩ, low-side 10mΩ, each with gate charge Qg = 10nC, 5V gate drive, a 20ns switching transition, 20ns dead time on each edge, and a body-diode forward voltage of 0.8V. Inductor DCR = 20mΩ.

The inductor's ripple current is ΔI = (Vin − Vout) × D ÷ (f × L) = 8.7 × 0.275 ÷ (500k × 4.7µ) ≈ 1.0A peak-to-peak, or 34% of the output current — a typical design value.

Working through each loss term

High-side conduction loss. On for a fraction D of the time, so I² × RDS(on) × D = 3² × 0.02 × 0.275 = 50mW. Strictly you'd use the RMS current including ripple, but at 34% ripple that only shifts the answer by about 1%.

Low-side conduction loss. On for (1 − D) of the time: 3² × 0.01 × 0.725 = 65mW. At a low duty cycle, the low side is on longer, so cutting the low-side RDS(on) has more leverage.

High-side switching loss. During the turn-on and turn-off transitions, voltage and current overlap. Approximating with 0.5 × Vin × Iout × (tr + tf) × f = 0.5 × 12 × 3 × 40n × 500k = 360mW — the single largest term in this example. The low side switches after its body diode has already taken over conduction (zero-voltage switching), so it carries almost no switching loss.

Gate drive loss. Qg × Vdrv × f, for both switches: 10n × 5 × 500k × 2 = 50mW. This is dissipated inside the controller IC.

Dead-time loss. While both MOSFETs are off, current flows through the low side's body diode. Vf × Iout × tdead × 2 × f = 0.8 × 3 × 20n × 2 × 500k = 48mW. Paralleling a Schottky diode lowers Vf and cuts this, though modern controllers already trim dead time down to a few ns, which limits how much that helps.

Inductor copper loss. I² × DCR = 9 × 0.02 = 180mW. The AC resistance from ripple (skin effect) is small at this frequency.

Inductor core loss. The flux swing from the ripple current dissipates power in the core material. This is normally worked out with the vendor's tool; for a ferrite core under these conditions it comes to roughly 50–100mW.

Output capacitor ESR loss. The RMS ripple current is ΔI ÷ √12 ≈ 0.29A. At 5mΩ ESR for a ceramic, that's a negligible 0.4mW; for an electrolytic (50mΩ ESR), 4mW.

Controller quiescent current. A few mA × Vin, or 20–50mW.

That's 0.86W of loss against 9.9W of output, or 92% efficiency. Broken down this way, the RDS(on)-driven conduction losses add up to only 115mW — 13% of the total — while switching loss and the inductor together take 70%. If you want more efficiency, look first at the MOSFET's transition time (gate resistance, driver strength, Qgd) and the inductor's DCR.

What happens when you raise the frequency

Raise the frequency from 500kHz to 2MHz and the same ripple only needs a quarter the inductance, 1.2µH — smaller, and you can shrink the output capacitor too. In exchange, every loss term proportional to frequency quadruples. In the example above: switching loss goes from 360mW to 1.44W, gate drive from 50mW to 200mW, dead-time loss from 48mW to 192mW, and core loss, at the same ripple, scales with frequency to roughly the 1.3–1.5 power.

The total climbs from 860mW to about 2.4W, and efficiency falls below 80%. Going to 2MHz still makes sense when size is the top priority, or when Vin is low enough that switching loss — proportional to Vin — stays small. At 5V input, the same calculation puts switching loss at under half of what it is at 12V.

Put the other way, switching at a high input voltage carries a large loss penalty, so generating 3.3V from 48V can end up more efficient as two stages — 48V→12V followed by 12V→3.3V — than as one.

Why efficiency falls off at light load

Drop the output current from 3A to 0.3A and conduction loss and copper loss fall to 1/100 (they scale with current squared) — but gate drive loss, controller quiescent current, part of the dead-time loss, and core loss all stay regardless of current. In the example above, that fixed share is around 150mW, which drags efficiency below 85% against just 1W of output.

There's also a wrinkle specific to synchronous rectification: once the inductor current dips below zero, current flows back out through the low side and circulates uselessly. Most controllers detect this at light load and either turn the low side off (diode emulation) or switch into a PFM mode that skips switching cycles. Under PFM, the fixed losses scale down with the (now lower) switching frequency, so efficiency can hold up even at loads of tens of mA.

When a battery-powered device draws more standby current than the numbers predict, the converter often simply isn't entering its light-load mode. Check the datasheet for the current threshold where it switches modes, and how much output ripple increases once it does.

Losses that come down to layout

Some losses never show up in the calculation. The loop formed by the input capacitor, the high side, and the low side (the hot loop) carries a current that jumps from 0 to 3A on every switching edge. Too much parasitic inductance in that loop puts a spike on the switch node, and absorbing it with a snubber or extra gate resistance adds loss of its own.

Minimize the area of the hot loop. Place the input capacitor right next to the MOSFETs and keep the loop closed within a single layer. Route the switch-node trace to the inductor by the shortest path and keep its area small — a larger area radiates more noise and couples capacitively into neighboring traces.

The synchronous buck converter calculator runs this article's loss calculation automatically from your input values. Use it to see how the losses shift as you change MOSFETs or frequency.