Why the last 5mm before an ESD protection diode defeats it

IEC 61000-4-2 8kV contact discharge: the standard fixes only the first ns

IEC 61000-4-2 has contact discharge, where an ESD gun discharges directly onto a metal part, and air discharge through the air. Contact discharge is what mostly matters for board design, and the standard defines its current waveform by the initial peak current and the rise time.

An 8kV contact discharge (level 4) has an initial peak current I_p ≈ 30A and a rise time t_r = 0.7 to 1ns. The current then continues for tens of ns, but what decides whether the TVS clamping voltage is exceeded and how much the path inductance to ground raises the voltage is the first 1ns or less. What matters is not distance on the board but the speed of this current.

di/dt is I_p ÷ t_r = 30A ÷ (0.7 to 1ns) ≈ 30 to 43A/ns, the number the next section multiplies by inductance. It is orders of magnitude faster than an 8/20µs surge (IEC 61000-4-5), and 1mm of inductance can no longer be ignored.

The branch stub and ground via add to the clamping voltage

The datasheet clamping voltage V_C is measured across the TVS itself and does not necessarily reach the IC pin as is. The inductance of the trace from the connector to the TVS does not raise the IC voltage. To the ESD current it is a series impedance on the source side, and it even slows the current's rise before it reaches the IC. How long that section is should be set by signal matching.

What raises the IC pin voltage is the inductance of the path where the current falls to ground. That means (a) the stub branching from the signal line to the TVS, plus the TVS's own ground side (pad, via, plane), and (b) with the IC between the connector and the TVS, the trace from the IC's branch point to the TVS. Most of the ESD current (30A class) takes this path, so the inductance L develops V = L × di/dt, which adds to the TVS terminal voltage and becomes the IC pin voltage. A guide is about 1nH/mm, and one via falls in this range. Check a via's value with the via inductance calculator.

Just 5mm of equivalent inductance in the stub and ground path pushes a fast unit (0.7ns) above 200V. Even with a clamping voltage near 20V, what reaches the IC pin is clamping voltage plus added voltage: 170 to 230V at 5mm equivalent and 320 to 450V at 10mm. Even with the TVS working, this greatly exceeds the IC's absolute maximum rating (usually a few V). The "5mm" in the title is this path just before the current reaches ground.

This is an idealized estimate, and the numbers shift with current distribution and how the IC's ground is taken, but it does show that "a low clamping voltage makes stub and ground path length irrelevant" does not hold.

Correct placement: the signal passes through the TVS pad

• Place connector, then TVS, then the protected part. With the TVS nearer than the IC, the ESD current falls to ground before it reaches the IC's branch point. In the reverse order (connector, IC, TVS), a large current flows in the trace from the IC's branch point to the TVS, and its inductance raises the IC voltage.
• Route the signal through the pad instead of using a branch stub. A T-shaped stub makes the whole stub length the inductance in the table. If the signal passes between the two pads, the stub disappears and only the ground-side path remains.
• Take the TVS ground to the plane by the shortest path. This is the top priority. Almost all the ESD current takes the path from the anode (ground side) to the plane. Put the ground via tight to the pad, and if possible directly under it (via in pad). If the ground side is long, shortening the signal-side stub does not reduce the added voltage.

Clamping voltage versus the IC's absolute maximum and its built-in ESD structure

The absolute maximum rating of most ICs is VDD ± 0.3 to 0.5V or a few V. The added voltage of 150 to 214V at 5mm equivalent is tens of times that or more. Many cases of an IC failing even though the TVS clamps, or becoming unstable later, are caused by this added voltage exceeding the rating.

The IC's built-in protection diodes are not designed to take system-level ESD alone. IC ESD robustness is based on component-level tests such as HBM and CDM, whose test currents are much smaller. The HBM (ANSI/ESDA/JEDEC JS-001) equivalent circuit discharges 100pF through 1.5kΩ, and even at 2kV the peak current is 2000V ÷ 1500Ω ≈ 1.33A with a 2 to 10ns rise. An 8kV contact discharge has a 30A peak and a rise under 1ns: more than 20 times the peak current and several times faster. The TVS's job comes before lowering the clamping voltage: it is to shunt the large current to ground outside the IC.

TVS dynamic resistance and reading TLP data

A TVS clamping voltage is not constant with current. In the I-V characteristic from a TLP (Transmission Line Pulse) test, voltage rises in proportion to current once the breakdown voltage V_BR is exceeded. The slope is the dynamic resistance R_dyn, and the clamping voltage is V_C = V_BR + R_dyn × I.

A TLP test (ANSI/ESDA STM5.5.1) sends short ns-scale pulses of increasing size and records voltage and current. At a speed close to ESD, it shows the true clamping voltage and dynamic resistance that 8/20µs surge tests and DC characteristics do not. If the datasheet gives "clamping voltage at I_PP" for several currents, you can back out R_dyn from the slope.

Even a TVS with a dynamic resistance of 0.3 to 1Ω adds R_dyn × I = 9 to 30V at 30A, which adds to the stub and ground path voltage in the table before it reaches the IC pin. Choose a TVS by its clamping voltage at high current (a small R_dyn) as well as a low V_BR.

A series resistor on the IC side shares the current

Even the shortest TVS placement does not bring the added voltage to zero. So a series resistor R_s (10 to 33Ω as a guide) is often placed between the TVS and the IC pin to limit the residual current flowing into the IC.

With the TVS-terminal node voltage V_node (clamping voltage plus the stub and ground path addition) and the IC's built-in protection diode forward voltage V_f ≈ 0.8V, the current into the IC is about I_IC = (V_node − V_f) ÷ R_s. For V_node = 20V, it falls to 1.9A with R_s = 10Ω, 0.9A with 22Ω, 0.6A with 33Ω and 0.2A with 100Ω. A larger R_s degrades the signal more (slower edges), so set it within what the signal allows.

This resistor does not replace the TVS: it limits what the TVS could not take to a current the IC's built-in structure survives. On a high-speed signal, R_s disturbs the line impedance, so confirm its value and position by measurement or similar.

Capacitance and signal speed: what TVS capacitance USB and HDMI allow

Seen from the signal line, a TVS is also a shunt capacitance to ground, which cuts bandwidth, worsens return loss and closes the eye. General guides are 1pF or less for USB 2.0 HS (480Mbps) and 0.3pF or less for the high-speed lanes of USB 3.x and HDMI. For low-speed signals such as UART, I2C and power lines, tens to hundreds of pF is no problem.

When a shunt capacitance C sits in the middle of a line terminated by 50Ω at both ends, the capacitor sees the two 50Ω in parallel, 25Ω. The −3dB corner is f = 1 ÷ (2π × 25Ω × C): about 6.4GHz for C = 1pF and about 21GHz for 0.3pF. A USB 2.0 HS edge is around 500ps (bandwidth 0.35 ÷ 500ps ≈ 700MHz), so even 1pF is not likely to cut the bandwidth.

High-speed lanes are still strict about capacitance because return-loss limits are set from frequencies far below the −3dB corner, the parasitic capacitance of the TVS package, pad and via adds on, and the eye margin at several Gbps is only tens of mV and a few ps.

For a high-speed lane TVS, in addition to clamping voltage and surge current, check the datasheet capacitance against the signal speed.

What catches people on real boards

A board that reboots when hit with an ESD gun, or does not change after adding a TVS, is common in designs where someone looked only at the clamping voltage and judged "within spec, so fine." Measure the branch stub length and ground via position, estimate the added voltage from the table, and if it is 5mm equivalent or more, suspect the layout. The typical case is a TVS hanging off a stub while the signal runs past the stub's root. If robustness suddenly drops in a new revision, check the Gerbers for changes such as a ground via moving away or a longer stub.

Protection that is weak only on a high-speed port comes from putting a general-purpose TVS of a few pF to a dozen pF on a USB 3.x or HDMI lane and closing the eye; switch to a low-capacitance part. Without a TLP system, measure the real length of branch point, TVS pad, ground via and plane in the Gerbers, estimate with the table, and if the margin is thin, revisit the layout before the part.