Power trace width: set by both temperature rise and voltage drop
Route a power trace off a table that says "0.3mm for 1A" and a long run will bite you with voltage drop. The width set by temperature rise and the width set by voltage drop are two separate calculations, and the longer the trace, the more the second one dominates.
Width from temperature rise: the IPC-2221 formula
Current through a trace dissipates I²R, and the temperature rises until that heat balances against what escapes. IPC-2221 gives an empirical formula for outer-layer traces, I = 0.048 × ΔT0.44 × A0.725 (I in A, ΔT in °C, A the cross-section in mil²). For inner layers the coefficient is half that, 0.024.
Solve that for 1oz copper (1.37mil, about 35µm) and a 10°C rise, and you get roughly 0.3mm at 1A, 0.8mm at 2A, 1.4mm at 3A, and 2.8mm at 5A. Allow a 20°C rise instead and the width drops to about 60% of that; go to 2oz copper and it's roughly half.
With half the coefficient, an inner layer works out to 2.6x the cross-section — and so 2.6x the width — for the same current. But that formula rests on measurements from the 1950s; the 2009 revision, IPC-2152, revises it, noting that an inner layer conducts heat to adjacent planes and the base material and can in practice carry as much current as an outer layer, or more. Treat the IPC-2221 inner-layer number as heavily conservative.
| Current | ΔT = 10°C | ΔT = 20°C | ΔT = 10°C, 2oz |
|---|---|---|---|
| 0.5A | 0.12mm | 0.08mm | 0.06mm |
| 1A | 0.30mm | 0.20mm | 0.15mm |
| 2A | 0.78mm | 0.51mm | 0.39mm |
| 3A | 1.37mm | 0.90mm | 0.69mm |
| 5A | 2.77mm | 1.82mm | 1.39mm |
| 10A | 7.3mm | 4.8mm | 3.7mm |
Width from voltage drop: length matters here
Length doesn't appear anywhere in the temperature-rise formula — heat generation and dissipation per unit length are the same whether the trace is long or short. Voltage drop, though, scales directly with length.
1oz copper foil has a sheet resistance of about 0.5mΩ/□ (at 20°C). A 0.3mm-wide, 100mm-long trace works out to 333 squares, or 167mΩ. Run 1A through it and it drops 167mV. On a 3.3V rail with a ±3% (100mV) budget, that alone blows the budget.
To size the width from voltage drop, get R = ΔV ÷ I from the voltage budget ΔV, then solve R = 0.5mΩ × L ÷ w for w. Keeping 1A over 100mm within 25mV needs R = 25mΩ, 50 squares, and w = 2mm — seven times the 0.3mm the temperature calculation gave.
As a practical rule of thumb, then: a short run (a few mm to around 10mm) is sized by temperature rise, a long run by voltage drop. The temperature formula is enough for the trace from an IC's power pin to its decoupling capacitor; a power rail crossing the board from a connector needs the voltage-drop calculation.
Surface plating on an outer layer typically brings 1oz copper up to 50–60µm finished, so the real sheet resistance runs 0.3–0.35mΩ/□. Recalculate with the fabricator's actual finished copper thickness and the voltage drop comes out 30–40% lower.
Copper resistance rises 40% with temperature
Copper's resistivity temperature coefficient is +0.39%/°C. Resistance calculated at 20°C runs 23% higher at 80°C and 39% higher at 120°C. As self-heating raises the trace's own temperature, resistance climbs too, pushing voltage drop and dissipation further upward.
Correct the resistance for the trace's actual operating temperature — ambient plus self-heating plus any nearby heat sources — in your design. The trace resistance calculator takes a temperature input, so run it at the maximum operating temperature.
Via current capacity
A via's conductor is a plated cylinder on the hole wall, 20–25µm thick. At a 0.3mm hole diameter and 25µm plating, the cross-section is π × 0.3 × 0.025 = 0.0236mm² (36mil²) — the same as a 0.68mm-wide trace in 1oz copper. The IPC-2221 formula puts that at about 1.5A for a 10°C rise.
At 1.6mm long, the resistance itself is small — 1.72×10⁻⁸ × 1.6mm ÷ 0.0236mm² ≈ 1.2mΩ — but current concentrates wherever the plating is thinnest, so calculate using the minimum plating thickness (say, 20µm) rather than the nominal value.
For 3A, use two or three vias in parallel; for 5A, four to six. Arrange them in a row across the width of the trace so the current splits evenly — put one via out in front of the rest and current concentrates there instead.
Copper pours and thermal relief
For anything over 1A, the standard practice is a copper pour rather than a discrete trace. It removes the width constraint entirely and lowers both voltage drop and heating. With four or more layers, dedicate an inner layer to a plane.
A through-hole pad tied to a pour gets thermal relief — thin cross-shaped spokes — to make it solderable. Those thin spokes (say, four legs of 0.3mm each) become the current path, so for high-current pads widen the spokes, or skip the relief and connect solidly, handling solderability with preheat instead.
Connector pins and fuse pads have failed in the field from the thin relief spokes heating up and degrading the solder. On a high-current pad, check the relief's total cross-section against the same criteria you'd use for a trace width.
Frequently asked questions
What width should a 1A power trace be?
Should I use IPC-2221 or IPC-2152?
For the same current, which is better, an outer layer or an inner layer?
Does the GND return path need the same width?
Standards and references
- IPC-2221B, Generic Standard on Printed Board Design — The conductor current-capacity formula (Section 6.2)
- IPC-2152, Standard for Determining Current Carrying Capacity in Printed Board Design — Measurement-based current-capacity charts, including the effect of inner layers and adjacent planes
- IPC-6012 — Plating thickness requirements for plated through-holes