RC filter cutoff frequency, and the attenuation you actually get

The -3dB point, and the slope beyond it

For a first-order low-pass made of a resistor R and a capacitor C, the cutoff frequency is f_c = 1 / (2πRC). With 1kΩ and 100nF that's 1.59kHz. At that frequency the output is 0.707x the input (-3dB).

Above the cutoff, every 10x increase in frequency costs another -20dB (1/10). That's -20dB at 10x f_c, -40dB at 100x. More precisely, |H| = 1 / sqrt(1 + (f / f_c)^2), giving -7dB at 2x f_c, -10dB at 3x, -14dB at 5x.

In other words, if the signal and the noise are only a decade apart in frequency, a first-order filter buys you 20dB. Two decades apart buys 40dB. Beyond that, your only options are raising the filter order (-40dB/decade with two stages) or separating the signal and noise frequencies further (lowering f_c).

It also acts on the signal

The filter affects the signal too. If the signal frequency is 1/10 of f_c, amplitude drops only 0.5% — but phase lags by 5.7°. That phase lag matters for a control loop's sensor signal, or for measurements across channels that need to stay synchronized. To keep amplitude error under 0.1% you need f_c at least 22x the signal frequency; to keep phase under 1° you need at least 57x.

In the time domain this shows up as settling time. For a step input, the output takes 4.6τ (τ = RC) to settle within 1% of its final value, and 6.9τ for 0.1%. With 1kΩ x 100nF = 100µs, 1% settling takes 460µs. If a multiplexer feeds an ADC across several channels, you need to wait this long after each switch or the previous channel's value bleeds through.

A filter that knocks 40dB off the noise is, equivalently, slowing the signal down 100x. Attenuation and response speed are set by the same RC, so you cannot improve one without the other.

The formula assumes specific source and load impedances

f_c = 1 / (2πRC) assumes a zero-impedance source and nothing connected to the output. In practice, the source's output resistance R_s adds in series with R, and the load's input resistance R_L appears in parallel with C.

If R_s is 1/10 of R or more, f_c shifts noticeably. A 10kΩ sensor output feeding an R = 10kΩ filter gives an effective R of 20kΩ, halving f_c. If R_L is only about 10x R, the DC gain drops to 0.9x and f_c rises.

As a rule of thumb, keep R_s ≤ R / 10 and R_L ≥ 10 × R. If that's not achievable, add buffers (op-amp voltage followers) before and after the filter.

When an RC sits at an ADC input, C also has to supply charge to the ADC's sampling capacitor. If C is 100x or more of the sampling capacitance (a few to a few tens of pF), the voltage sag during sampling stays under 1%. From that angle, a bigger C is better, and R should stay at or below the input impedance the ADC requires.

The capacitor's self-resonance caps the real attenuation

The math might say -56dB at 1MHz, but a real 100nF capacitor may not even behave like a capacitor at 1MHz. A 1608 100nF MLCC resonates in series with about 0.5nH of ESL, and its impedance bottoms out around 20MHz; above that it behaves like an inductor. Attenuation caps there and actually gets worse as frequency climbs further.

A 10µF part resonates lower still, around 2MHz; a 1nF part around 200MHz. Bigger capacitors run out of steam at lower frequencies, so if you need both a low f_c and high-frequency attenuation, put a large and a small capacitor in parallel (the same issue as supply decoupling — watch for anti-resonance).

Resistors have a similar limit: high values (100kΩ and up) get bypassed at high frequency by their own lead-to-lead stray capacitance (0.1-0.5pF). 100kΩ with 0.2pF creates a zero at 8MHz, above which attenuation stalls.

For knocking down noise above a few tens of MHz, LC (ferrite bead plus capacitor) usually beats RC — a ferrite bead turns resistive at high frequency and doesn't have this resonance problem.

Cascading two stages

If one stage isn't enough, add a second. But simply repeating the same R and C loads the first stage with the second, shifting f_c and keeping the slope short of -40dB/decade. Make the second stage's R at least 10x the first's (and C 1/10), so the later stage doesn't load the earlier one — for example, 1kΩ + 100nF followed by 10kΩ + 10nF.

Putting a buffer between the stages lets you reuse the same R and C. It costs one more op-amp, but removes the impedance interaction and gives you the response you designed for.

If you need a sharper roll-off, a second-order active filter built with an op-amp (Sallen-Key, for example) uses fewer parts than cascaded passive RC stages and also lets you set Q.

RC on digital signals: debouncing

A 10kΩ + 100nF RC (τ = 1ms) is the standard trick for switch debouncing, but it comes with a catch. The signal through the RC rises slowly, so the input lingers near the threshold for a while. On an ordinary CMOS input, that can make the logic level flip back and forth repeatedly, or draw through-current.

Feed an RC-slowed signal into a Schmitt-trigger input. Many microcontroller GPIOs are Schmitt-trigger, but check the datasheet. For an input with no hysteresis, put something like a 74HC14 in between.

The RC filter calculator computes the cutoff frequency from R and C, plus the attenuation and phase at a given frequency. Enter the noise frequency, check how many dB it actually drops by, and then settle on R and C.