RC filter cutoff frequency, and the attenuation you actually get

The -3dB point, and the slope beyond it

For a first-order low-pass of a resistor R and a capacitor C, the cutoff frequency is f_c = 1 / (2πRC). With 1kΩ and 100nF that is 1.59kHz, where the output is 0.707x the input (-3dB).

Above the cutoff, every 10x in frequency costs another -20dB. More precisely, |H| = 1 / sqrt(1 + (f / f_c)^2); the values are in the table below.

If the signal and the noise are only a decade apart, a first-order filter buys you 20dB, and two decades buys 40dB. Beyond that, raise the order or lower f_c.

It also acts on the signal

If the signal frequency is 1/10 of f_c, amplitude drops only 0.5%, but phase lags by 5.7°. That matters for a control loop's sensor signal, or for measurements that need channels synchronized. For amplitude error under 0.1% you need f_c at least 22x the signal frequency; for phase under 1°, at least 57x.

In the time domain this is settling time. For a step input, the output takes 4.6τ (τ = RC) to settle within 1% of its final value, and 6.9τ for 0.1%. With 1kΩ x 100nF (τ = 100µs), 1% settling takes 460µs, so after each multiplexer switch to an ADC, wait that long or the previous channel bleeds through.

A filter that knocks 40dB off the noise slows the signal down 100x.

The formula assumes specific source and load impedances

f_c = 1 / (2πRC) assumes a zero-impedance source and nothing on the output. In practice the source's output resistance R_s adds in series with R, and the load's input resistance R_L appears in parallel with C.

If R_s is 1/10 of R or more, f_c shifts noticeably: a 10kΩ sensor output feeding R = 10kΩ gives an effective R of 20kΩ and halves f_c. If R_L is only about 10x R, the DC gain drops to 0.9x and f_c rises. Keep R_s ≤ R / 10 and R_L ≥ 10 × R, or add buffers before and after the filter.

C at an ADC input should be 100x or more of the sampling capacitance (a few to a few tens of pF) to keep the voltage sag under 1%.

The capacitor's self-resonance caps the real attenuation

The math may say -56dB at 1MHz, but a real 100nF capacitor may not be a capacitor at 1MHz. A 1608 100nF MLCC resonates in series with about 0.5nH of ESL, its impedance bottoms out around 20MHz, and above that it is an inductor. Attenuation caps there and gets worse as frequency climbs.

A 10µF part resonates around 2MHz and a 1nF part around 200MHz, so bigger capacitors run out of steam sooner. For both a low f_c and high-frequency attenuation, put a large and a small capacitor in parallel (watch for anti-resonance). High resistances (100kΩ and up) are bypassed by stray capacitance (0.1 to 0.5pF): 100kΩ with 0.2pF creates a zero at 8MHz, above which attenuation stalls.

Above a few tens of MHz, LC (ferrite bead plus capacitor) usually beats RC.

Cascading two stages

Repeating the same R and C for two stages loads the first with the second, shifting f_c and keeping the slope short of -40dB/decade. Make the second stage's R at least 10x the first's (and C 1/10), for example 1kΩ + 100nF then 10kΩ + 10nF.

A buffer between the stages lets you reuse the same R and C. For a sharper roll-off, use a second-order active filter such as Sallen-Key.

RC on digital signals: debouncing

A 10kΩ + 100nF RC (τ = 1ms) is the standard trick for switch debouncing, but the signal rises slowly, so the input lingers near the threshold. On an ordinary CMOS input that can make the logic level flip back and forth, or draw through-current.

Feed an RC-slowed signal into a Schmitt-trigger input. Check the datasheet, and put something like a 74HC14 in front of an input with no hysteresis.

The RC filter calculator gives the attenuation and phase at the noise frequency, so check it before settling on R and C.