Resistor divider error: how far tolerance and loading push you from the design value
A divider built from R1 and R2 scales the voltage by R2/(R1+R2) on paper. In practice, tolerance, the load's input resistance, temperature and the ADC's sampling capacitor move the output a few percent, so check that the divider is not adding more error than the ADC's resolution.
Two ±1% resistors: a worst case of ±2% on the divider ratio
The error in the divider ratio R2 ÷ (R1 + R2) is largest when R1 and R2 drift in opposite directions. R1 at +1% and R2 at −1% pushes the ratio down; the reverse pushes it up.
For R1 = R2 (a 1/2 divider), 0.99 ÷ (1.01 + 0.99) = 0.495, or −1% against 0.5. For R1 = 9·R2 (a 1/10 divider), 0.99 ÷ (9.09 + 0.99) = 0.0982, or −1.8%. The smaller the divider ratio, the closer the error gets to ±2%. As a formula, relative error ≈ ±(R1 tolerance + R2 tolerance) × R1 ÷ (R1 + R2).
One LSB on a 12-bit ADC is 0.024% of full scale, so a 2% error is 82LSB.
The fixes are 0.1% resistors (ratio ±0.2%), calibration at manufacture with the measured ratio stored in firmware, or a design that does not need absolute accuracy, as in threshold detection.
| Resistor tolerance | Worst-case ratio error | Equivalent LSB (12-bit ADC) |
|---|---|---|
| ±5% | ±9.0% | ±370LSB |
| ±1% | ±1.8% | ±74LSB |
| ±0.5% | ±0.9% | ±37LSB |
| ±0.1% | ±0.18% | ±7LSB |
The load's input resistance lands in parallel with R2
The input resistance RL of whatever is connected to the divider output lands in parallel with R2 and pulls the ratio down. Load an R1 = R2 = 100kΩ divider with RL = 1MΩ and R2 ∥ RL = 90.9kΩ, so the ratio is 90.9 ÷ 190.9 = 0.476, or −4.8%.
To keep the error under 0.1%, make RL at least 1000 times R2. For R2 = 100kΩ that means RL = 100MΩ, where you would add an op-amp buffer. Making R2 smaller instead raises the divider current.
A SAR ADC connects a small capacitor (a few pF to a few tens of pF) to the divider output during sampling. If R1 ∥ R2 is high, the capacitor cannot fully charge within the sampling time and the reading comes in low. Keep R1 ∥ R2 within the datasheet's input-impedance limit, or put a 10 to 100nF capacitor at the output, though too large a time constant stops it tracking the input.
Power dissipation and voltage rating: dividing a high voltage
Dividing 48V down to 4.8V with R1 = 90kΩ, R2 = 10kΩ draws 0.48mA and dissipates 21mW in R1, which is fine. With R1 = 9kΩ, R2 = 1kΩ the current is 4.8mA and R1 dissipates 207mW. That exceeds a 1608 (0603)'s 100mW rating, and a 3216 (1206, 250mW) falls short once you apply derating.
Voltage rating is also easy to overlook. The maximum working voltage of a chip resistor is commonly 50V for a 1005, 75V for a 1608, 150V for a 2012 and 200V for a 3216, and a part with more than its rating across it is unusable whatever its resistance. A 1608 as R1 in a 100V divider sees 90V, over its 75V rating.
Splitting R1 into two or three resistors in series is standard for high voltage. It spreads voltage and power, and limits the output jump if one resistor fails short.
Temperature coefficient acts on the ratio
A chip resistor's temperature coefficient is ±100 to 200ppm/°C, up to ±1% over a 50°C swing. But the ratio depends on the difference between the R1 and R2 coefficients, and resistors of the same series and material barely change it. Trouble comes from mixing types (thick-film with thin-film, or different sizes) or from R1 alone self-heating in a high-voltage divider. With 0.1% resistors, match R1 and R2 as thin-film parts of ±25ppm/°C or better.
A resistor network with R1 and R2 in one package (ratio accuracy ±0.05%, coefficient mismatch ±5ppm/°C, for example) beats individual 0.1% resistors on ratio, and both halves stay at the same temperature.
Noise and leakage at high resistance
High resistance such as R1 = 1MΩ, R2 = 100kΩ cuts power but brings other problems. Thermal noise is 40nV/√Hz for 100kΩ, or 4µVrms over 10kHz: small next to a 12-bit ADC's 1LSB (0.8mV on 3.3V full scale), but it starts to matter at 16 bits (50µV). Board leakage matters too: flux residue or humidity puts tens to hundreds of MΩ in parallel with R2, and 100MΩ across a 100kΩ R2 is a 0.1% error.
Input bias current also counts. With a bipolar-input op-amp, or an ADC input leakage as high as 1µA, 1µA through R1 ∥ R2 = 90kΩ is a 90mV error (a CMOS input's few pA is negligible). A high-impedance node also picks up external noise, so add a capacitor at the output or keep the trace short.
Keeping the divider current between 10µA and 1mA balances these issues against power. For 3.3V that is a total of 3.3kΩ to 330kΩ.
Frequently asked questions
For an accurate divider ratio, what tolerance of resistor should I use?
Can a divider's output go straight into an MCU's ADC?
Can I use a 1608 resistor for R1 in a 48V divider?
Going to higher resistance saves power. Is there a ceiling?
Standards and references
- IEC 60115-8 — Rated power, maximum working voltage, and temperature coefficient specifications for chip resistors
- MCU vendors' datasheets and reference manuals — The relationship between ADC input impedance and sampling time, and input leakage current
- Analog Devices, MT-004: The Good, the Bad, and the Ugly Aspects of ADC Input Noise — The relationship between front-end noise and resolution in ADC circuits