Why USB PD always starts at 5 V

Why it does not just put out 20 V

The same Type-C connector fits a device that only ever takes 5 V at 0.5 A and a laptop that takes 20 V at 5 A. Either way round, too.

So at the moment of plugging in, the source does not know what the other end can survive. Put 20 V on the pins and the first person to plug in a 5 V-only device destroys it.

USB PD fixes the order instead. Put out 5 V only (vSafe5V, 4.75–5.5 V). Move to anything else only after the two ends have agreed and the sink has explicitly asked for it. The voltage never rises except in response to a request from the sink.

What the resistors settle before anyone talks

The first stage has no protocol in it at all. Whether something is attached, which way round the cable is, and how much current may be drawn at 5 V are all decided by a resistive divider on CC1 and CC2.

The source pulls CC up through Rp; the sink pulls it down through Rd = 5.1 kΩ. From the source's side, whichever CC got pulled down is the one that is actually connected, and that is how orientation is resolved.

From the sink's side, the CC voltage is itself the advertisement of how many amps it may take at 5 V.

The useful consequence is that you can take up to 5 V at 3 A with no PD silicon at all — one 5.1 kΩ resistor and an ADC on CC. Anything above 5 V, though, requires the protocol.

The other CC belongs to the cable. A cable with an eMarker pulls that line down with Ra (800 Ω – 1.2 kΩ); when the source sees Ra it powers that pin as VCONN and talks to the chip inside the cable. Carrying 5 A requires this eMarker.

The order of the negotiation

Once 5 V is up, the rest happens as messages over CC, in a fixed order.

1. Source_Capabilities: the source lists what it can provide (5 V/3 A, 9 V/3 A, 20 V/5 A, …)
2. Request: the sink picks one entry and asks for it
3. Accept: the source agrees. Nothing has moved yet.
4. PS_RDY: sent once the voltage has actually settled at the new value

Every message is acknowledged with a GoodCRC from the receiver. That only confirms delivery; it is not agreement about the contents.

Each step has a time limit. Waiting for the other end's reply is tSenderResponse, 24–30 ms in PD 2.0 and 27–33 ms in PD 3.0. From sending Accept to starting to move the voltage is tSrcTransition, 25–35 ms. Completing the transition is tPSTransition, 550 ms at most.

The interval that matters is between Accept and PS_RDY — that is when the voltage is moving. The sink has an obligation here too: during that window it has to drop its load to the lower of the old and new contracts. Ask for 20 V and immediately pull full current, and the source cannot raise the rail.

Going up versus coming down

Both directions get the same 550 ms, but they are not equally hard.

Going up, the source actively pushes current into VBUS and the sink's input capacitance. How long it takes is a property of the source, which makes it straightforward.

Coming down is the awkward one. A source can supply current but cannot necessarily absorb it. How fast 20 V falls to 5 V depends on the total capacitance on VBUS and on how much current the load happens to be drawing. If the sink has gone into a low-power state and is taking a few milliamps, the rail barely moves.

That is why sources that can step down almost always contain a discharge path — a FET that pulls VBUS down actively. Leave it out and you get a fault that only appears at light load, which is the worst kind to reproduce.

When you test this, test the step-down at light load. A heavy load discharges the rail for you and hides the problem.

When it goes wrong: Hard Reset

When the negotiation breaks, PD does not resume from where it was. It starts over, and that is a Hard Reset.

The source takes VBUS down to vSafe0V (below 0.8 V), which must happen within tSafe0V, 650 ms. Then it waits tSrcRecover (660–1000 ms) before putting vSafe5V back up. Everything restarts from 5 V.

Power is fully off for the better part of a second, so the sink drops out. Chasing "the device reboots occasionally when I use this charger" usually ends up here.

Things that catch you out in design

• The sink's input capacitor gets charged. Going 5 V to 20 V, the input capacitance takes the charge for ΔV. 100 µF over a 15 V step is 1.5 mC — 2.7 mA averaged over 550 ms, but far more instantaneously if the source ramps quickly.
• Keep 5 V circuitry from ever seeing 20 V. Bring up the downstream rails only after the requested voltage has arrived. Driving a load switch from the PD controller's PS_RDY-equivalent output is the clean way.
• A cable without an eMarker stops at 3 A. Carrying 5 A needs the chip in the cable. Designing for 20 V at 5 A and testing with a 3 A cable is a common mix-up.
• The voltage is not always fixed. PPS (Programmable Power Supply) lets the sink ask in 20 mV steps. Convenient as a charger, but from the load's point of view it is a supply whose voltage moves.
• There is a version that goes to 48 V. PD 3.1 EPR adds 28 V, 36 V and 48 V, up to 240 W. It differs from SPR (up to 20 V) from the entry handshake onwards, so treat it as a separate thing.