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Why USB PD always starts at 5 V

If 20 V appeared the moment you plugged in, every 5 V-only device would die on first contact. USB PD avoids that with a stage settled by resistors alone, and a stage where nothing moves until the sink asks.

Last updated: 2026-10-28 USB PDType-CPower sequencingProtocol

Why it does not just put out 20 V

The same Type-C connector fits a device that only takes 5 V at 0.5 A and a laptop that takes 20 V at 5 A, in either orientation. So when you plug in, the source does not know what the other end can survive.

USB PD fixes the order. The source puts out 5 V only (vSafe5V, 4.75 to 5.5 V), and moves to another voltage only after the two ends have agreed and the sink has explicitly asked. The voltage rises only in response to a request from the sink.

A USB-C device and power supply checking their power-delivery requirements
A USB-C device and power supply checking their power-delivery requirements. AI-generated conceptual illustration; see the article’s diagrams and text for circuit details and conditions.

What the resistors settle before anyone talks

The first stage has no protocol. Whether something is attached, which way round the cable is, and how much current may be drawn at 5 V are decided by a resistive divider on CC1 and CC2.

The source pulls CC up through Rp, and the sink pulls it down through Rd = 5.1 kΩ. The CC that gets pulled down is the connected one, which resolves orientation, and the CC voltage is the advertisement of how many amps may be drawn at 5 V.

Rp, the CC voltage, and the current allowed at 5 V
Source Rp (pull-up to 5 V)Equivalent current sourceCC voltage at the sinkAllowed current
56 kΩ80 µA0.20–0.66 VUSB default (0.5 A / 0.9 A)
22 kΩ180 µA0.66–1.23 V1.5 A
10 kΩ330 µAabove 1.23 V3.0 A

So you can take up to 5 V at 3 A with no PD silicon.

A cable with an eMarker pulls the other CC down with Ra (800 Ω to 1.2 kΩ); the source powers that pin as VCONN and talks to the chip. Carrying 5 A requires the eMarker.

The CC pins on USB Type-CThe source pulls CC1 up to 5 volts through Rp and the sink pulls it down through a 5.1 kilohm Rd. The resulting divider voltage on CC advertises how much current is allowed at 5 volts. The other CC is pulled down by the cable eMarker through roughly 1 kilohm of Ra, and the source powers that pin as VCONN once it sees it. The table on the right: 56 kilohm gives 0.20 to 0.66 volts and USB default current, 22 kilohm gives 0.66 to 1.23 volts and 1.5 amps, 10 kilohm gives above 1.23 volts and 3 amps. What resistors settle before any communication Attachment, cable orientation and the current allowed at 5 V are all decided here Source Sink Cable 5V Rp CC1 Rd 5.1k = the advertisement CC2 / VCONN Ra 1k Rp and the current advertised 56k (80uA) CC 0.20-0.66V USB default 0.5A / 0.9A 22k (180uA) CC 0.66-1.23V 5V 1.5A 10k (330uA) CC above 1.23V 5V 3.0A No PD silicon is needed up to here. Only going above 5V requires messages on CC CC1 and CC2 are separate pins. The source switches whichever one shows Ra over to VCONN to power the chip in the cable (required for 5A)
Figure 1: CC1 is an Rp/Rd divider, CC2 carries the cable's Ra and VCONN.

The order of the negotiation

Once 5 V is up, the rest happens as messages over CC.

  1. Source_Capabilities: the source lists what it can provide (5 V/3 A, 9 V/3 A, 20 V/5 A, ...)
  2. Request: the sink picks one entry and asks for it
  3. Accept: the source agrees. The voltage has not moved yet.
  4. PS_RDY: the source sends this once the voltage has settled at the new value

Each step has a time limit. Waiting for a reply is tSenderResponse: 24 to 30 ms in PD 2.0, 27 to 33 ms in PD 3.0. From Accept to the start of the voltage change is tSrcTransition: 25 to 35 ms. Finishing the transition is tPSTransition: 550 ms at most.

The voltage moves between Accept and PS_RDY, and in that window the sink has to drop its load to the lower of the old and new contracts. Ask for 20 V and immediately pull full current, and the source cannot raise the rail.

The USB PD negotiation sequenceA graph of VBUS voltage against time. From an unattached 0 volts it rises to 5 volts when attachment is detected, and at that voltage the Source_Capabilities, Request and Accept messages are exchanged. After Accept the source waits 25 to 35 milliseconds, then raises the voltage, reaching 20 volts within at most 550 milliseconds, and sends PS_RDY. What happens, in what order, between 5 V and the voltage you asked for The voltage moves after Accept. The signal that it arrived is PS_RDY 0 5V 20V VBUS attach detected, 5V Source_Capabilities Request (20V) Accept PS_RDY tSrcTransition 25-35ms transition, tPSTransition max 550ms blue: sent by the source green: sent by the sink The time axis is not to scale; drawn to scale it would be almost entirely the 5V section
Figure 2: VBUS and the order of messages on CC. The time axis is not to scale.

Going up versus coming down

Going up, the source charges VBUS and the sink's input capacitor, so the time is set by the source's design.

Coming down is the awkward one. A source can supply current but cannot necessarily absorb it, so how fast 20 V falls to 5 V depends on the capacitance on VBUS and the current the load draws. A sink in a low-power state taking a few milliamps leaves the rail barely moving.

Sources that can step down usually have a discharge path, a FET that pulls VBUS down. Without it, the fault appears only at light load and is hard to reproduce.

When you test, check the step-down at light load. A heavy load discharges the rail for you and hides the problem.

USB PD voltage transitions and Hard ResetOn the left, stepping up: after Accept the source waits 25 to 35 milliseconds and then reaches 20 volts within 550 milliseconds. On the right, stepping down, with two curves comparing a heavy load that falls quickly against a light load where the output capacitance is not discharged and the rail does not reach 5 volts. Below, a Hard Reset: VBUS falls to vSafe0V within 650 milliseconds, then after 660 to 1000 milliseconds the source restarts at 5 volts. Going up and coming down are not equally hard Going up (5V to 20V) 5V 20V arrive within 550ms wait 25-35ms Up: the source charges actively, so the time is a property of the source Coming down (20V to 5V) 5V 20V heavy load: falls quickly light load: does not get there Down: the source cannot sink current. The load discharges VBUS, so at light load it may not make the deadline Hard Reset: start again from 5V 5V 20V Hard Reset to vSafe0V within 650ms tSrcRecover 660-1000ms restart at vSafe5V
Figure 3: going up, the source pushes; coming down, it depends on the load. Bottom: Hard Reset.

When it goes wrong: Hard Reset

When the negotiation fails, PD does not resume from where it was. It starts over, and that is a Hard Reset.

The source takes VBUS down to vSafe0V (below 0.8 V) within tSafe0V, 650 ms, waits tSrcRecover (660 to 1000 ms), and restarts from vSafe5V. Power is off for nearly a second, so the sink drops out.

Inrush into the input capacitor

Going from 5 V to 20 V, the sink's input capacitance takes a charging current for the ΔV. 100 µF over a 15 V step is 1.5 mC, or 2.7 mA averaged over 550 ms, and far more if the source ramps quickly.

VBUS ramp speed and input capacitor charging currentLeft: two ways of raising VBUS from 5 volts to 20 volts, slowly over 550 milliseconds or quickly in a shorter time. Right: the charging current into the input capacitor. The slow ramp gives a low, long shape averaging 2.7 milliamps; the fast ramp gives a tall, short shape with a far larger instantaneous current. The area, which is the charge, is the same 1.5 millicoulombs in both (100 microfarads, 15 volt step). Charging current into the input capacitor, 5V to 20V VBUS voltage 5V 20V fast ramp ramp over 550ms time Charging current average 2.7mA instantaneous: far larger time Area = charge, the same 1.5mC in both (100uF, 15V step)
Figure 4: for the same charge, the faster the ramp, the larger the charging current.

Easy-to-miss points in design

  • Keep 5 V circuitry from ever seeing 20 V: switch on the downstream rails from the PD controller's PS_RDY-equivalent output, after the requested voltage has arrived.
  • A cable without an eMarker stops at 3 A, a common mix-up when designing for 20 V at 5 A (100 W).
  • With PPS (Programmable Power Supply) the sink asks in 20 mV steps, so the load sees a supply whose voltage moves.
  • PD 3.1 EPR adds 28 V, 36 V and 48 V (up to 240 W) and differs from SPR (up to 20 V) from the entry handshake onwards.

Frequently asked questions

Can I take power from Type-C without a PD controller?
At 5 V, yes. Put 5.1 kΩ from each of CC1 and CC2 to ground and read the CC voltage to see whether 0.5 A, 1.5 A or 3.0 A is allowed.
I got an Accept but the voltage did not change.
Accept only means the request was agreed. PS_RDY is the signal that the voltage has arrived.
It only fails when stepping down.
Suspect a step-down at light load. The source cannot sink current, so a light load leaves VBUS undischarged and it may miss tPSTransition (550 ms).
I designed for 100 W and only get 60 W.
Look at the cable. Without an eMarker it stops at 3 A, and 20 V × 3 A = 60 W.

Standards and references

  • USB Power Delivery Specification (USB-IF) — Message definitions and the tSenderResponse / tSrcTransition / tPSTransition / tSrcRecover timings
  • USB Type-C Cable and Connector Specification (USB-IF) — Rp / Rd / Ra values, the CC voltage thresholds, VCONN and eMarkers
  • USB Power Delivery Compliance Test Specification (USB-IF) — Measurement conditions for each timing

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