How to size an I²C pull-up: the VOL/IOL floor and the bus-capacitance ceiling

Open-drain means the resistor sets the rise

SDA and SCL on I²C are open-drain: a device can only pull the line low. Bringing it back to high is the pull-up resistor's job. Going from low to high, R_p charges the bus capacitance C_b, so the rise time follows the time constant R_p·C_b.

A smaller resistor rises faster but forces the device to sink more current when it pulls low. A larger resistor draws less current but rises more slowly. The floor is set by current, the ceiling by rise time.

The I²C spec sets the sink current I_OL at V_OL = 0.4V to 3mA for Standard/Fast mode, and caps the rise time t_r (30%→70%) at 1000ns for Standard mode, 300ns for Fast mode, and 120ns for Fast mode Plus. Bus capacitance is capped at 400pF.

The floor: can 3mA pull it below 0.4V?

When a device pulls the line low, the current fed in through the pull-up is (V_DD − V_OL) ÷ R_p. Exceed the spec's 3mA sink current and the device can no longer guarantee V_OL at or below 0.4V.

R_p(min) = (V_DD − 0.4V) ÷ 3mA. That's 967Ω at V_DD = 3.3V, or 1.53kΩ at 5V. Nothing smaller will work. A device rated for Fast mode Plus can sink up to 20mA, which pushes the floor as low as 145Ω at 3.3V.

If any device on the bus can't sink 3mA (a lower I_OL in its datasheet), recompute the floor using that value instead.

The ceiling: does the rise time fit?

For an RC charge, the time from 30% to 70% is t_r = R_p · C_b · ln(0.7 ÷ 0.3) ≈ 0.847 · R_p · C_b. From the spec's t_r ceiling, R_p(max) = t_r(max) ÷ (0.847 · C_b).

At 100pF bus capacitance, the ceiling is 11.8kΩ for Standard mode (1000ns), 3.5kΩ for Fast mode (300ns), and 1.4kΩ for Fast mode Plus (120ns). Use 4.7kΩ at 3.3V in Fast mode, and you're already over the ceiling at just 100pF.

Bus capacitance is the sum of each device's pin capacitance (under 10pF by spec, typically 5–10pF in practice), the board traces (0.5–1pF/cm), and any cable (50–100pF/m). Five devices, 20cm of trace, and 30cm of cable comes to about 50 + 15 + 25 = 90pF. Each ESD protection diode adds a few more pF.

R_p range at 3.3V (floor from 3mA, ceiling from each mode's t_r limit)
Bus capacitance	Standard 100kHz	Fast 400kHz	Fast+ 1MHz
50pF	0.97k–23.6kΩ	0.97k–7.1kΩ	0.15k–2.8kΩ
100pF	0.97k–11.8kΩ	0.97k–3.5kΩ	0.15k–1.4kΩ
200pF	0.97k–5.9kΩ	0.97k–1.8kΩ	0.15k–0.7kΩ
400pF	0.97k–3.0kΩ	Not possible*	0.15k–0.35kΩ

* The ceiling (0.9kΩ) falls below the floor (0.97kΩ), so no value works. At the spec's maximum 400pF, Fast mode simply can't rise fast enough within the 3mA sink limit. In practice, keep the bus under 200pF, split it, or add a buffer IC.

Figure 1: the valid range for an I²C pull-up at 3.3V. The floor is a flat line set by the 3mA sink current; the ceiling is a curve that falls as bus capacitance rises. Green marks where Fast mode works.

Where in the range to land

Anything between the floor and the ceiling works, but where you land trades off power against noise immunity.

Smaller resistor (toward the floor). Faster rise, better immunity to external noise, but more current while pulled low. At 3.3V, 1kΩ means 2.9mA, or up to 6mA with both SDA and SCL low at once. With a 50% duty clock, SCL alone averages 1.5mA — not negligible on battery power.

Larger resistor (toward the ceiling). Lower power, but the rise time sits right at the spec limit, so temperature drift or adding another device can push it out of range. The high impedance also picks up more noise.

In practice, picking a half to a third of the ceiling leaves margin for errors in your capacitance estimate or for adding devices later. At 3.3V, Fast mode, 100pF, that lands around 1.5–2.2kΩ; for Standard mode, 4.7kΩ remains a reasonable choice.

Things that catch you out

Pull-ups built into modules. Many off-the-shelf sensor modules carry their own 4.7kΩ or 10kΩ pull-up. Connect five of them and five 4.7kΩ resistors in parallel becomes 940Ω, below the floor. Remove the pull-ups from the modules, or skip the one on the MCU side.
The MCU's internal pull-up. A GPIO's built-in pull-up is 20–50kΩ, far too weak for I²C — it will not rise in time at 400kHz. Use an external one.
Level shifting. Mixing 3.3V and 5V devices with a MOSFET-based level shifter (the NXP AN10441 approach) needs a pull-up on each side. Calculate the floor and ceiling separately for each voltage.
Measure the rise, don't assume it. Check the SCL rise on a scope and confirm the 30%→70% time has margin against the spec limit. If the edge is rounded enough that the next low arrives before it reaches high, lower the resistor or cut the capacitance.
Clock stretching. If a slave stretches the clock, SCL becomes bidirectional too, and a master driving SCL push-pull will collide with it. Make SCL open-drain as well.

Frequently asked questions

So what value should I actually use at 3.3V?

For a small on-board bus at 100kHz (two or three devices), 4.7kΩ is fine. At 400kHz, aim for 2.2kΩ, or 1.5kΩ if the bus is larger than 100pF. If you're running a cable, estimate the bus capacitance and recompute the ceiling.

Can SDA and SCL use different resistor values?

Yes. SCL toggles continuously so it matters more for power, but the rise-time requirement is the same for both. Most designs use the same value, though some make SCL slightly smaller for a faster clock edge.

Where should the pull-up physically sit?

Electrically, anywhere on the bus is equivalent. In practice, put it near the master so the pull-up stays in place even if other devices (a plug-in module) are removed. On a long bus, splitting it between both ends is fine too — just calculate the combined parallel value.

What if bus capacitance exceeds 400pF?

Split the bus and bridge it with an I²C multiplexer or buffer (a PCA9515, for example), or use an I²C extender IC that runs the cable segment differentially. Forcing the rise time down with a smaller resistor just pushes you below the floor, and devices can no longer pull the line low.

Standards and references

NXP UM10204, I²C-bus specification and user manual — Specified values for V_OL / I_OL, t_r, and C_b, and the pull-up sizing formula (Section 7.1)
NXP AN10441, Level shifting techniques in I²C-bus design — MOSFET-based level-shifting circuit
TI SLVA689, I²C Bus Pullup Resistor Calculation — Worked examples of the floor and ceiling calculation