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Choosing an I²C pull-up: between a floor and a ceiling

4.7kΩ is a rule of thumb from 5V, 100kHz, small buses; at 3.3V and 400kHz with five modules and a 30cm cable it can't keep up. The resistor has a floor and a ceiling, both calculable.

Last updated: 2026-10-30 I²CPull-up resistorOpen-drainBus capacitance

Open-drain means the resistor sets the rise

SDA and SCL on I²C are open-drain: a device can only pull the line low. Bringing it back to high is the pull-up resistor's job. Going from low to high, Rp charges the bus capacitance Cb, so the rise time follows the time constant Rp·Cb. A smaller resistor rises faster but draws more sink current.

The main example below uses a resistive pull-up at 3.3V and a 3mA sink specification at VOL = 0.4V for Standard/Fast-mode. Maximum 30–70% rise times are 1000ns, 300ns and 120ns for Standard, Fast and Fast-mode Plus. Bus-capacitance limits differ: 400pF for Standard/Fast and 550pF for Fast-mode Plus. Also check each device's voltage conditions and drive capability.

A pull-up resistor helping a signal rise
A pull-up resistor helping a signal rise. AI-generated conceptual illustration; see the article’s diagrams and text for circuit details and conditions.
Current on an open-drain bus when returning high and when pulled lowLeft: returning high. The device MOSFET is OFF and current from VDD through Rp charges the bus capacitance Cb. Right: pulled low. The MOSFET is ON and the device sinks the current from VDD through Rp to ground. An open-drain bus has two current paths The device only pulls low. The pull-up brings it back high Returning high VDD Rp SDA/SCL Cb OFF Rp charges Cb Rise follows the time constant Rp·Cb Ceiling: rise time Pulled low VDD Rp SDA/SCL Cb ON The device sinks current Current is (VDD − VOL) ÷ Rp Floor: 3mA sink current
Figure 1: when low, the device sinks the current fed through Rp; when returning high, Rp charges Cb.

The floor: can 3mA pull it below 0.4V?

When a device pulls the line low, the current fed in through the pull-up is (VDD − VOL) ÷ Rp. Above the spec's 3mA sink current, VOL at or below 0.4V is no longer guaranteed.

Rp(min) = (VDD − 0.4V) ÷ 3mA. That's 967Ω at VDD = 3.3V, or 1.53kΩ at 5V; nothing smaller will work. A Fast mode Plus device can sink up to 20mA, pushing the floor down to 145Ω at 3.3V. For a device that can't sink 3mA, use its IOL.

The ceiling: does the rise time fit?

For an RC charge, the time from 30% to 70% is tr = Rp · Cb · ln(0.7 ÷ 0.3) ≈ 0.847 · Rp · Cb. From the spec's ceiling, Rp(max) = tr(max) ÷ (0.847 · Cb).

At 100pF bus capacitance, the ceiling is 11.8kΩ for Standard mode (1000ns), 3.5kΩ for Fast mode (300ns), and 1.4kΩ for Fast mode Plus (120ns). Use 4.7kΩ at 3.3V in Fast mode, and you're over the ceiling at 100pF. 4.7kΩ keeps up only to about 250pF in Standard mode and 75pF in Fast mode.

Rise for two pull-up values, and the 30%→70% timeRise at 100pF bus capacitance. The Rp = 3.5kΩ curve keeps 30%→70% within Fast mode's 300ns limit; the Rp = 4.7kΩ curve does not. Rise is measured as the 30%→70% time Fast mode allows 300ns. A larger Rp misses it VDD 30% 70% Limit 300ns (Fast mode) Over 300ns Rp = 3.5kΩ Rp = 4.7kΩ Cb = 100pF tr = 0.847 · Rp · Cb At 3.3V, Fast mode, 100pF, 4.7kΩ is over the limit.
Figure 2: at 100pF, Rp = 3.5kΩ keeps 30%→70% within Fast mode's 300ns; 4.7kΩ does not.

Estimating bus capacitance, and the valid range

Bus capacitance is the sum of each device's pin capacitance (under 10pF by spec, typically 5–10pF), the board traces (0.5–1pF/cm), and any cable (50–100pF/m). Five devices, 20cm of trace, and 30cm of cable make about 50 + 15 + 25 = 90pF; each ESD diode adds a few pF.

For Fast mode at 3.3V the valid range is 0.97k–3.5kΩ at 100pF and 0.97k–1.8kΩ at 200pF. At 400pF there is none: the ceiling (0.9kΩ) is below the floor (0.97kΩ). Keep the bus under 200pF, split it, or add a buffer IC. The no-overlap result at 400pF applies specifically to this 3.3V, 3mA, 300ns passive-resistor model.

I²C pull-up: floor and ceilingA log-log chart, bus capacitance 20-400pF on the x-axis and resistance 100Ω-30kΩ on the y-axis. A flat line at the 967Ω floor, with ceiling curves for Standard, Fast, and Fast mode Plus, and the valid region for Fast mode shaded. The 4.7kΩ point is also marked. Pick Rp between the floor line and the ceiling curve VDD=3.3V; floor assumes 3mA, not the Fast+ 20mA case 20pF50pF100pF200pF400pF 100Ω1kΩ10kΩ Pull-up Rp Bus cap Cb Standard (1000ns) Fast (300ns) Fast+ (120ns) Floor 967Ω (3mA at 0.4V) 4.7kΩ Valid for Fast mode 4.7kΩ works up to ~250pF in Standard mode, but only ~75pF in Fast mode. Fast mode, 100pF ceiling 3.5kΩ; with margin, pick 1.5–2.2kΩ. At 400pF the Fast ceiling falls below the floor. Split the bus or add a buffer.
Figure 3: the valid range at 3.3V. The floor is a flat line set by 3mA; the ceiling falls as bus capacitance rises. Green marks where Fast mode works.

Where in the range to land

Being inside the interval satisfies this resistor/capacitance model, not every communication requirement. Also check voltage compatibility, clock High/Low times, level shifters and all device specifications. Smaller resistance speeds charging but increases Low-state current; its tolerance corner must stay above the lower bound.

Rather than selecting a fixed fraction of the upper bound, check rise time at maximum resistance/capacitance and current at minimum resistance/maximum supply. Choose lower capacitance, a different resistor or a lower bus rate according to which constraint fails.

Include tolerance and pull-ups already fitted to modules

At 3.3V, 100pF, Fast-mode, IOL = 3mA and VOL = 0.4V, the nominal window is about 967Ω–3.54kΩ. A single 2.2kΩ ±5% resistor spans 2.09–2.31kΩ; its slow corner gives about 196ns. At 150pF that becomes about 294ns, leaving little margin to 300ns. At 200pF it reaches about 391ns, so this resistor exceeds the rise-time limit.

Five modules each carrying 4.7kΩ ±5% pull-ups give a combined 893–987Ω. At 893Ω the current is (3.3 − 0.4) / 893 ≈ 3.25mA, outside the assumed 3mA condition. Use the parallel combination of every fitted pull-up: maximum supply/minimum resistance for Low-level current, maximum resistance/capacitance for rise time.

Things that catch you out

  • Pull-ups built into modules. Many carry their own 4.7kΩ or 10kΩ; five 4.7kΩ in parallel is 940Ω, below the floor. Remove them, or skip the MCU-side one.
  • The MCU's internal pull-up. At 20–50kΩ it is too weak for I²C. Use an external one.
  • Level shifting. A MOSFET-based shifter for mixed 3.3V and 5V (the NXP AN10441 approach) needs a pull-up on each side; calculate floor and ceiling per voltage.
  • Clock stretching. If a slave stretches the clock, make SCL open-drain too; a push-pull master collides.

Frequently asked questions

So what value should I actually use at 3.3V?
For the assumed 3.3V, Fast-mode, 100pF and 3mA case, 2.2kΩ ±5% meets the resistor/RC limits. At 200pF its worst rise is about 391ns and fails. Recalculate using actual capacitance, parallel pull-ups and every device's guaranteed sink current.
Where should the pull-up physically sit?
Electrically, anywhere is equivalent. Near the master it stays if a module is unplugged; if you split it between both ends, use the combined parallel value.
What if bus capacitance exceeds 400pF?
Split the bus with an I²C multiplexer or buffer (e.g. PCA9515), or use an extender IC that runs the cable differentially. A smaller resistor just pushes you below the floor.

Standards and references

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