Can a SOT-23 LDO deliver 300mA from 5V to 3.3V? Thermal resistance depends on copper area

0.51W looks small, but the junction exceeds 150°C

An LDO's dissipation is the sum of what the pass element burns and the IC's own supply current (quiescent current I_Q): P = (V_in − V_out) × I_out + V_in × I_Q. For 5V to 3.3V at 300mA that is (5 − 3.3) × 0.3 = 0.51W, and with I_Q of tens to 100µA, 5V × 60µA ≈ 0.3mW is negligible.

Multiplying this 0.51W by the package's thermal resistance θ_JA (junction to ambient) gives the temperature rise. For a SOT-23-5, θ_JA is about 200°C/W under JEDEC's high-conductivity board condition (it varies widely by package and maker). ΔT = 0.51W × 200°C/W ≈ 102°C, and at an ambient of 50°C (typical inside an enclosure) the junction reaches 50 + 102 = 152°C. Many LDOs have T_J(max) of 125°C, so this is 27°C over the rating.

"It can deliver 300mA" and "the junction exceeds 150°C" are both true because the datasheet's output current is set by the pass element's current capability alone, regardless of θ_JA. The thermal limit must be checked separately with θ_JA and your own board and ambient temperature.

θJA is not a number for your board

θ_JA is measured on a specific test board defined by JEDEC JESD51-7 (the "high-conductivity board" or "2s2p board": four layers, with large copper planes on the two inner layers), and exists to compare packages with each other. On a two-layer board with little copper, a board with other heat sources nearby, or one with a split plane, the real θ_JA is normally worse (larger) than the datasheet value. Conversely, thermal vias that drain heat into an inner GND plane can bring it closer to the datasheet value. Do not calculate once with θ_JA and stop; confirm on real hardware with the method in the next section.

ΨJT and ΨJB: estimating junction temperature from a measured surface temperature

You cannot put a thermometer in the junction, so you work back from temperatures you can measure. The coefficients are Ψ_JT (junction to top of package) and Ψ_JB (junction to board).

T_J = T_top + Ψ_JT × P (from the top-of-package temperature), or T_J = T_board + Ψ_JB × P (from the board temperature right next to the IC). Whereas θ_JA holds only under defined test conditions, the Ψ values are coefficients that JEDEC JESD51-12 defines so that they can be used as an approximation under real conditions (your board, your cooling); they are not thermal resistances themselves. Ψ_JT is a single digit to about ten-odd °C/W, far smaller than θ_JA (hundreds of °C/W).

There are three steps. (1) Measure the top of the package, or the board copper right next to the IC, with a thermal camera or a fine thermocouple (painting the surface matte black avoids emissivity scatter). (2) Find the dissipation P at that time (measured ideally, calculated if that is hard). (3) Multiply by the datasheet Ψ_JT or Ψ_JB and add.

Copper area and thermal resistance: it helps up to a few cm², then levels off

Copper acts as a heat sink: it spreads heat sideways from under the IC through the leads and releases it to the air over its area. A larger area lowers θ_JA, but the first few cm² help most and beyond that the effect fades quickly, because heat meets resistance spreading through the copper and copper far from the IC contributes little. The table below is a guide for SOT-23-size packages (it varies with board and copper thickness, so read it as a trend).

The table shows that widening the copper does not lower θ_JA without limit. Past a few cm², what helps next is not more area but thermal vias that carry heat into an inner GND plane. The temperature rise from copper follows the same reasoning as choosing power trace width by temperature rise and voltage drop.

Thermal vias: count, diameter, plating, and the inner GND plane

A thermal via bypasses heat that top-side copper alone cannot remove into inner or bottom copper. The effect depends on the number of vias, their diameter and plating thickness, and the resistance of one via can be estimated from the plating (copper) cross-section and the board thickness as R = L ÷ (k × A), where k (thermal conductivity of copper) ≈ 385W/(m·K) and A is the plating cross-section (π × diameter × plating thickness for an unfilled via).

A single via in a 1.6mm board with 0.3mm diameter and 35µm plating (1oz equivalent) is about 126°C/W. Thermal resistances in parallel divide by the number of vias, and a larger diameter, thicker plating (2oz, or resin fill plus plating) lowers it further.

These figures are the via's own resistance; the real path also has the spreading resistance from the top copper to the via entrance and from the inner or bottom copper to the air in series. Even so, just 4 to 9 vias of 0.3mm diameter under the IC can often give a lower resistance than gaining top-side area, which makes it the most effective step on a SOT-23 layout with limited board area.

An inner GND plane not only receives heat but spreads it over its whole area before it reaches the enclosure or the back side. If the plane is split or shared with other heat sources, this effect weakens.

Changing the package: SOT-23, SOT-223 and DFN with exposed pad

Before squeezing the board with copper and vias, it is worth asking whether the package must be a SOT-23-5 at all. Moving to a package built for heat can help more than board tricks.

Just changing from SOT-23-5 to SOT-223 or DFN can improve θ_JA by 3 to 5 times. But a DFN's exposed pad works only if the board provides thermal vias and enough copper. With no vias under the pad, the result is little better than a SOT-23.

When thermal protection trips, the output cycles

The symptom is an output voltage that drops periodically, or a load that resets intermittently. An LDO has built-in thermal shutdown: when the junction exceeds the threshold (150-165°C in many parts) it switches the output off, and once it has cooled by the hysteresis (about 10-30°C) it restarts, heats up and cuts out again, repeatedly. From the load, the supply seems to drop out every few to tens of seconds.

The protection is working as designed, but it is also a sign that the thermal design cannot carry that current continuously, and left alone it shortens part life. If the symptom goes away when the load is reduced, heat is the cause, and a cycle that gets shorter as the load rises is typical. On the datasheet look at the thermal shutdown threshold, hysteresis, θJA and ΨJT / ΨJB.

Putting a series resistor at the input to share the heat

A simple way to cut the LDO's dissipation is to put a resistor between the input and the LDO to take over part of the voltage drop. In the 5V-to-3.3V, 300mA example, R_s = 3.3Ω drops 3.3Ω × 0.3A = 0.99V ≈ 1V. The LDO input becomes 4V and its dissipation is (4 − 3.3) × 0.3 + 4 × I_Q ≈ 0.21W, 60% less.

The 0.3W saved has just moved into the resistor (0.99V × 0.3A ≈ 0.3W), and the total system loss barely changes. It works because the dissipation goes to a part that is allowed to get hot and has the heat-spreading area the IC package cannot have. Use a large chip resistor with power rating to spare (several in parallel, or a wirewound, also work).

There are two cautions. (1) The resistor lowers the LDO's input voltage, so check that the LDO's dropout voltage is still met at maximum load current. (2) The drop across the resistor depends only on current, so when the input voltage falls (battery operation, for example) the LDO's burden rises directly. It suits a fixed input and a nearly constant load.

Where to switch to a DC-DC

With θ_JA and the copper and vias your board can provide, working back the maximum dissipation from ambient temperature and allowable junction temperature keeps the decision steady. The guide is P_max = (T_J(max) − T_A) ÷ θ_JA.

If the dissipation for your current and voltage difference has little margin against this table, or exceeds it, it will be hard however much you work on copper and vias. As a guide, at about 70°C ambient inside an enclosure with a SOT-23-class package, 0.3-0.4W of continuous dissipation is about the practical limit for a linear regulator. Beyond that (5V to 3.3V at 500mA or more, 12V to 3.3V at 100mA or more, and so on), change to SOT-223 or DFN, or switch to a synchronous buck converter (see synchronous rectification and forced PWM). A buck converter is typically 85-95% efficient, with a loss of a fraction to a tenth of the linear regulator's. If the loss is only 0.1-0.2W, tidying copper and vias on the LDO is enough.

The input resistor only moves where the heat is generated, while a DC-DC raises efficiency and reduces the absolute loss.

Steps to confirm on hardware

1. Calculate the design dissipation P for the expected voltages and currents (P = (Vin − Vout) × Iout + Vin × IQ), and estimate the junction temperature at the worst ambient with the datasheet θJA. The power consumption calculator can check this. If there is little margin against TJ(max), consider copper, vias, a package change or a DC-DC at this point.
2. When a prototype exists, measure the IC surface or the board temperature next to it with a thermal camera or thermocouple, and estimate the junction temperature with ΨJT and ΨJB.
3. Run at the worst conditions (maximum load, highest ambient, no airflow) for several to ten-odd minutes and check that the output voltage does not drop periodically. If margin is short, compare the effect and cost of these in order: more copper, then thermal vias, then a package change, then an input resistor, then a DC-DC.