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SRAM, DRAM, NOR, NAND, EEPROM, FRAM, MRAM, eMMC: memory types and how to choose

There's no memory that is "non-volatile, rewritable, and fast" all at once. Every memory gives up endurance, capacity, speed, or price, so this is organized to be looked up by application.

Last updated: 2026-10-28 MemoryFlashEEPROMeMMC

Start with three groups

It helps to split memory into three groups: volatile memory that loses its contents when power is removed (SRAM, DRAM); the flash family that keeps its contents and stores electrons in a floating gate (NOR, NAND, eMMC, EEPROM); and the newer non-volatile types that keep their contents and can be written byte by byte (FRAM, MRAM). Except for EEPROM, the flash family erases in blocks.

Choosing a memory type for an application
Choosing a memory type for an application. AI-generated conceptual illustration; see the article’s diagrams and text for circuit details and conditions.
The three groups of memory and how the names nestMemory split into three groups: volatile, flash family, and newer non-volatile. In the volatile group, SDRAM sits inside DRAM and DDR sits inside SDRAM. In the flash family, NOR and NAND are grouped as flash, NAND plus a controller is eMMC, and the byte-writable variant is EEPROM. The newer non-volatile group has FRAM and MRAM. Three groups and how the names relate SDRAM is a kind of DRAM; eMMC is NAND inside Volatile Flash family Newer non-volatile SRAM 6-transistor flip-flop DRAM 1 transistor + 1 capacitor SDRAM DRAM synchronous to a clock DDR Generations of SDRAM DDR to DDR5, low-power LPDDR Flash Umbrella term for NOR and NAND NOR NAND eMMC NAND + Controller EEPROM Same principle, byte-writable FRAM Stored as ferroelectric polarization MRAM Stored as magnetization direction
Figure 1: the three groups and how the names nest. SDRAM is a kind of DRAM, and DDR is its generation name. eMMC is NAND inside.

Comparing capacity and endurance

Memory comparison (typical ranges; varies a lot by part)
TypeVolatileCapacityWrite granularityEnduranceWrite time
SRAMYesFew kB–few MBByteUnlimitedFew ns
DRAM / SDRAM / DDRYes64MB–few GBByte (burst)UnlimitedTens of ns
NOR flashNo1MB–256MBWrite: byte, erase: sector (4k–64kB)100k cyclesWrite µs, erase 100s of ms
NAND flash (raw)No1GB–few TBWrite: page (few kB), erase: block (MB)SLC 100k, TLC 3kWrite 100s of µs, erase few ms
eMMCNo4GB–256GBSector (512B, NAND inside)Managed by controller100s of µs+
EEPROMNo1kbit–4MbitByte1M cycles5ms (page)
FRAMNo4kbit–16MbitByte10¹⁴ cyclesTens of ns (no wait)
MRAMNo1Mbit–1GbitByteUnlimited (10¹⁵+)Tens of ns
Capacity vs. endurance by memory typeA scatter plot with capacity (1kbit–1Tbit) on the x-axis and endurance (10³–10¹⁶ cycles) on the y-axis, marking the regions for SRAM, DRAM, MRAM, FRAM, EEPROM, NOR, NAND, and eMMC as boxes. High capacity and unlimited endurance don't coexist Typical ranges by part. Volatile memory's "unlimited" endurance is plotted at 10¹⁶ 1kbit 1Mbit 1Gbit 1Tbit 10³ 10⁶ 10⁹ 10¹² 10¹⁵ Endurance Capacity SRAM DRAM / DDR MRAM FRAM EEPROM NOR NAND eMMC Volatile (lost on power-off) Flash family (limited cycles) Byte-writable non-volatile
Figure 2: capacity vs. endurance. The top-right corner (high capacity and high endurance) doesn't exist.

Volatile: SRAM and DRAM

SRAM is a flip-flop, six transistors per bit. It needs no refresh and reads and writes in a few ns. The cell is large, so capacity tops out at tens to hundreds of kB on-chip and a few MB external.

DRAM is one transistor and one capacitor per bit. The charge leaks, so it must be read and rewritten (refreshed) every few tens of ms. The cell is small, so gigabytes are cheap. A memory controller on the processor side handles refresh and timing, so a microcontroller without one cannot connect to DRAM. Processors that run Linux have a DDR controller.

The rule of thumb is simple: SRAM for a few MB or less, DRAM above that. The middle ground of a few MB is filled by QSPI pseudo-SRAM (PSRAM, DRAM inside with refresh built in).

The flash family: NOR, NAND, EEPROM, eMMC

Flash stores data by trapping electrons in a floating gate. Writing (adding electrons) can be done bit by bit, but erasing (removing electrons) can only be done in a larger block. Most of the differences below follow from that.

NOR flash connects its cells in parallel, so any address can be read at random. The processor can execute instructions straight from it (XIP, Execute In Place), which makes it the home for boot code. An erase takes hundreds of ms.

NAND flash chains its cells in series to pack in more density. Bit errors are routine, so ECC and bad-block management are mandatory. Endurance is 100k cycles for SLC, 10k for MLC, 3k for TLC, and 1k for QLC: more bits per cell is cheaper but weaker.

eMMC puts a controller on top of NAND that handles ECC, wear leveling, and bad-block management internally. From the outside it just reads and writes 512B sectors, and it's the standard home for a Linux root filesystem.

EEPROM is small non-volatile memory that erases and writes byte by byte. A write takes about 5ms, but it survives a million cycles. It holds settings, calibration data, and serial numbers.

Write unit and erase unit in flashWrite and erase units for NOR, NAND, and EEPROM. In NOR, byte-sized write units sit inside one sector (4kB to 64kB) that is erased as a whole. In NAND, page-sized write units (a few kB) sit inside one block (hundreds of kB to a few MB). In EEPROM, both erase and write are byte-sized. Writes are small, erases are large Not to scale. In NOR and NAND, an erase always takes the whole block NOR Erase: sector (4kB–64kB) Write: byte NAND Erase: block (100s of kB to few MB) Write: page (few kB) EEPROM Erase and write: both a byte A write can turn a 1 into a 0. Turning a 0 back into a 1 needs an erase.
Figure 3: write unit and erase unit in flash.

FRAM and MRAM: byte-writable non-volatile memory

FRAM (ferroelectric RAM) stores data as the polarization direction of a ferroelectric material. It writes byte by byte with no wait (write cycle of tens of ns) and survives 10¹⁴ write cycles. There's no 5ms write wait like EEPROM, and a power loss mid-write doesn't corrupt the data. Capacity tops out around 16Mbit and it costs more than EEPROM.

MRAM (magnetoresistive RAM) stores data as the magnetization direction of a magnetic layer. Endurance is effectively unlimited, and some parts match SRAM's speed and interface, which is why it's used to replace battery-backed SRAM. It reaches the 1Gbit class, but costs tens of times more than DRAM.

Both suit applications that write often, may lose power unexpectedly, and don't need much capacity. Doing the same in flash needs wear leveling and power-loss protection, and adding one FRAM chip usually costs less.

Choosing by application

Choosing memory by application
ApplicationChoiceReason and caveats
Boot code / firmwareOn-chip MCU flash; QSPI NOR if that's not enoughSupports XIP and fast random reads. With NAND, add a small NOR or use eMMC's boot partition
Working memoryOn-chip SRAM up to a few hundred kB; PSRAM or external SRAM for a few MB; DDR above thatDDR assumes a processor with a memory controller
Settings / calibration data (written a few times a year to a few times a day)I²C EEPROMOn-chip flash emulation works too, but calculate the erase count and granularity
Running totals / counters / state (written every second to every minute)FRAM or MRAMWritten every second, EEPROM uses up its million cycles in about two weeks
Logs / measurement data (large volume, append-only)SPI NAND, eMMC, or an SD cardRaw NAND means providing your own ECC and bad-block management
An OS filesystemeMMCSD cards bring insertion/removal wear and quality risk
The last-known state that must survive a power lossFRAM or MRAMA power loss mid-write doesn't corrupt the data

Common mistakes

  • Writing to flash every second hits the erase-cycle limit within a day or two. Erasing a 4kB sector every time you rewrite 16 bytes of settings also ends the part's life at 100k cycles. Buffer in RAM and write less often, implement wear leveling (rotate the write location within the sector), or keep settings in a separate EEPROM or FRAM.
  • An EEPROM doesn't respond during its 5ms write window. Wait with ACK polling.
  • If power drops during a write, both flash and EEPROM leave the page in an undefined state. Write alternately to two locations and pick the valid one by CRC, or use FRAM.
  • Raw NAND has bad blocks from the factory and bits flip in use, so ECC is mandatory even for SLC.
  • eMMC is TLC NAND inside, with a cap on total bytes written (TBW). For frequent logging, calculate the lifespan and consider SLC mode or an industrial-grade part.
  • DDR3 and above need length matching, controlled impedance, and termination, which is tough on a 4-layer board. Consider a module (SOM).
  • Some MRAM parts corrupt data near a magnet (speaker, relay, Hall sensor). Check the datasheet's field immunity.

Frequently asked questions

What's the difference between EEPROM and flash?
Both store electrons in a floating gate. EEPROM erases byte by byte, with low capacity (up to a few Mbit) and 1M cycles; flash erases in sectors or blocks, with high capacity and low cost but 100k cycles or fewer.
Are SDRAM and DDR different things?
DDR is a kind of SDRAM. In embedded contexts, "SDRAM" on its own usually refers to the older SDR SDRAM (3.3V, around 133MHz).
What's the difference between eMMC and an SD card?
The internals (NAND plus a controller) are nearly identical. eMMC is a soldered BGA part with a boot partition, aimed at production. SD cards are removable but come with quality variation and contact risk.
Should I choose FRAM or MRAM?
FRAM for low capacity (a few Mbit or less) at lower cost; MRAM for higher capacity or an SRAM-compatible parallel interface.

Standards and references

  • JEDEC JESD79 series / JESD84 (eMMC) — DDR SDRAM and eMMC standards
  • ONFI (Open NAND Flash Interface) specification — Raw NAND interface and ECC requirements
  • Individual memory vendors' datasheets — Endurance, data retention, write time, TBW

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