Why is a clock crystal 32.768kHz? The reason it isn't built to output 1Hz directly

32768 = 2 to the 15th power

Divide 32768 by 2 and you get 16384; divide again and you get 8192; keep going and you land on 1 at exactly the 15th division. That's because 32768 = 2¹⁵. Given a crystal that vibrates 32768 times a second, repeating a "count only every other one" operation 15 times over yields a pulse once per second.

A "count only every other one" circuit is about as simple as electronics gets. A single toggle switch that flips its output on every input edge turns two input cycles into one output cycle — the frequency is halved. Chain fifteen of these in series and that's the divider: a few hundred transistors, tucked into a small corner of a clock IC.

Use a decimal-friendly crystal like 10000Hz or 100000Hz instead, and you need a circuit that counts "one in ten." That's more complex than "one in two," and it takes more stages. Stick to a power of two and all you need is the simplest circuit, repeated. That's the first reason behind the odd number "32768."

So why not just make a 1Hz crystal?

Rather than stacking fifteen halving stages, it seems like it would be simpler to build a crystal that vibrates once a second to begin with. There are reasons it can't be built, and reasons it isn't.

It's too large to build. A crystal's frequency is set by the dimensions of the crystal blank. A clock crystal is shaped like a tuning fork, and a tuning fork vibrates more slowly as its arms get longer. Frequency is inversely proportional to the square of the arm length, so dropping the frequency to 1/32768 needs arms √32768 ≈ 181 times longer. A 32.768kHz fork has arms around 3mm, so a 1Hz fork would need arms over 50cm — it won't fit in a wristwatch. Long arms also sag under gravity or vibration, which destabilizes the frequency. Crystals are only practical to build above roughly 10kHz.

It couldn't be trimmed. Crystals vary by around ±20ppm from part to part, which works out to ±1.7 seconds a day. Correcting for that means occasionally counting one extra pulse, or skipping one. At 32768Hz, skipping one out of the 32768 counted each second gives a 1/32768 = 30.5ppm correction, and skipping one every few tens of seconds fine-tunes below 1ppm. With a 1Hz crystal, the smallest adjustable unit is "one second" — a 100% correction. Counting a fast vibration is exactly what makes fine adjustment possible.

Timing finer than one second is needed. Sounding an alarm tone, measuring 1/100 second on a stopwatch, waking a microcontroller every 1/256 second — a clock has plenty of tasks that need less than a second. The 256Hz and 1024Hz points partway through halving down from 32768Hz are directly usable. A 1Hz crystal can't produce anything shorter than a second.

Start-up takes time. A crystal needs tens of thousands of cycles from the moment it starts oscillating until its amplitude settles (a consequence of its high Q). Even at 32.768kHz that's 0.5–2 seconds, a known drawback of clock crystals. A 1Hz crystal would need the same number of cycles, which comes to several hours. A clock that takes half a day to start after you insert the battery isn't usable.

Jitter averages out. Each individual cycle carries a small amount of timing jitter. Because the one-second pulse is the result of counting 32768 cycles, the individual jitters add up and cancel, leaving the one-second pulse's jitter at 1/√32768 ≈ 1/181 of a single cycle's jitter. The faster the vibration being counted, the more accurate the one-second pulse.

There are ways to generate 1Hz without a crystal (an RC oscillator, charging and discharging a resistor-capacitor pair), but their accuracy is only 1% to a few percent. 1% works out to a 15-minute drift per day — useless for a clock. A crystal's ±20ppm is more than 500 times more accurate than that.

So why not go with a higher frequency instead?

If 1Hz is off the table, a fast crystal like 4MHz or 10MHz seems just as viable — that's exactly what's used for microcontroller clocks. The reason it isn't used for a clock comes down mainly to the battery.

Current draw is proportional to frequency. A CMOS circuit draws current every time a signal switches. A 32.768kHz oscillator plus divider runs on 0.3–1µA combined. A CR2032 coin cell (225mAh) could theoretically run it for 25+ years, and in practice lasts 5–10 years. Run the same circuit at 4MHz and the current jumps by more than 100x, leaving the battery only a few weeks. That's decisive for a wristwatch, or for the backup battery of an RTC that keeps time with the power off.

The tuning-fork type is small and cheap. The 32.768kHz tuning-fork crystal, in production for wristwatches since 1969, is the highest-volume crystal made anywhere. Today it comes in a 2.0mm × 1.2mm package for a few cents. MHz-range crystals are a different part entirely — flat plates (AT-cut) with a different shape and different temperature behavior.

It sits above the audible range. Human hearing tops out around 20kHz. A 32.768kHz fork is physically vibrating but inaudible. Early wristwatch crystals used 8192Hz and 16384Hz too, but a lower frequency means both a bigger crystal and a frequency that falls inside the audible range. Just above 20kHz, a power of two, with low enough current draw — that intersection is 32768Hz.

Quirks of the 32.768kHz crystal

That covers why it was chosen, but there are quirks worth knowing on the design side too.

Temperature only ever pulls it slow. A tuning-fork crystal's frequency peaks near 25°C and falls off in proportion to the square of the temperature difference from there (around −0.035ppm/°C²). At 0°C or 50°C, 25°C away in either direction, that's −22ppm, or −1.9 seconds a day. Whether it's hot or cold, the clock runs slow. High-precision RTC ICs (the DS3231, for example) correct for this with a temperature sensor and hold ±2ppm.

Load capacitance shifts the frequency. If the capacitors across the crystal (the load capacitance, 6pF or 12.5pF) drift from spec, the frequency shifts with them. A 1pF error moves it by around 10ppm, so it has to be matched including the board's stray capacitance. A microcontroller's RTC typically has a calibration register that numerically corrects for such a 1pF-equivalent shift, adding or removing a few pulses over 32 seconds for ±0.5ppm steps — another adjustment made possible only by counting a fast vibration.

The oscillation is weak, and vulnerable to noise and leakage. To keep current draw down, the oscillator is driven very gently. The traces around the crystal are high-impedance, so coupling from an adjacent signal line or leakage current from flux residue on the board surface can stop the oscillation or shift its frequency. Standard practice is to place the crystal right next to the IC, keep the traces as short as possible, surround it with GND, and route no other signal underneath it.

Start-up is slow. As noted, 0.5–2 seconds. RTC initialization needs a step that waits for the oscillation to settle (an LSERDY flag or similar on a microcontroller's RTC), and the clock doesn't advance for the first few seconds after a battery change.

In summary: the advantage of counting

To produce one second, the design counts 32768 fast cycles rather than using a one-second oscillator. This "counting" approach comes with the benefits of fine trimming, finer time intervals for free, and averaged-out jitter — and the circuit is nothing more than "count every other one," repeated 15 times.

And the counting speed settled on 32768Hz — a power of two, inaudible, sitting between the lower bound of what a crystal can be built at (the tens of kHz) and the upper bound the battery can sustain (below 100kHz). It looks like an odd number, but it's close to the only value that satisfies every constraint at once.

For estimating current draw and battery life, use the mAh→Wh calculator and the power consumption calculator; for converting between frequency and period, use the frequency ⇔ wavelength calculator.