A bigger RC in front of an ADC is not always better: sampling-capacitor kickback

The sample switch and the sampling capacitor

Inside the pin of a SAR (successive approximation) ADC there is usually only a sample switch (on-resistance of a few hundred Ω to a few kΩ) and the sampling capacitor C_sh connected to it (a few pF in an MCU). In the sample (acquisition) period the switch is closed and C_sh charges or discharges toward the pin voltage. In the hold (conversion) period the switch opens, and the SAR digitizes only the voltage on the isolated C_sh by binary search.

What the ADC measures is not the input voltage itself but how far C_sh settled by the end of the sample period. If the source has a resistance R (a divider, the sensor's internal resistance and so on), C_sh charges along a first-order RC curve with R, and whatever has not settled appears in the code as a systematic error, not as noise.

How many τ to settle within 1/2 LSB: 9τ at 12 bits

The error of a first-order RC falls as e^−t/τ (τ = R·C) over time t. To settle within 1/2 LSB at N bits, the error must be at most V_ref/2^N+1, so

the condition is t/τ ≥ ln(2^N+1) = (N+1)·ln2, that is, e^−t/τ ≤ 1/2^N+1. In node, 12 bits (N = 12) gives ln(2¹³) ≈ 9.01, which is where the rule "9τ at 12 bits" comes from.

Connecting a high-resistance divider directly: 100kΩ/100kΩ battery monitoring

A circuit that divides a lithium battery voltage by 100kΩ/100kΩ and feeds the ADC directly is common. The source resistance (Thevenin resistance) is 50kΩ, and with C_sh = 5pF, τ = 250ns and the time to settle at 12 bits is 9τ ≈ 2.25µs.

Yet because people want short sample times, many MCUs end up with something near the default, t_acq = 1µs. In node, t_acq/τ = 4 and the remaining error is e⁻⁴ ≈ 1.83%, about 75LSB at 12 bits (4096 codes), or about 60mV at V_ref = 3.3V.

This is a systematic error that always leans toward the not-yet-settled side, so no amount of averaging removes it. It is separate from divider tolerance and loading errors (see the resistor-divider error article): it is an error of simply not having enough time.

Reading the datasheet's "allowed source resistance"

Many MCU datasheets have a table of maximum source resistance R_AIN(MAX). It is a value paired with the sample time (number of cycles) you set: the longer the sample time, the larger the allowed R_AIN. Read it as a combined condition, "with this sample time, keep the source resistance below so many Ω."

Easy to miss is switching channels on a multiplexer. Right after the switch, C_sh still holds the previous channel's voltage, so the difference to settle is the voltage difference between channels (worst case, full scale).

Adding an external capacitor: charge-sharing arithmetic

When you cannot lengthen the sample period or lower the source resistance, the standard fix is an external capacitor C_ext right at the ADC pin. C_ext acts as a reservoir, so the fast charge exchange when the switch closes does not have to pass through the source resistance R.

Charge sharing between C_ext and C_sh follows from charge conservation. When C_ext is much larger than C_sh, the node voltage moves by about C_sh/(C_sh + C_ext) after sharing. To make that at most 1/2^N+1, equal to 1/2 LSB, C_ext ≥ C_sh·(2^N+1 − 1) ≈ C_sh·2^N+1 is the guide. For 12 bits and C_sh = 5pF, node gives C_ext ≥ about 41nF.

In practice people pick an X7R of 0.1µF (100nF) for margin, where C_sh/(C_sh + 100nF) ≈ 5×10⁻⁵, less than half the threshold 1/2¹³ ≈ 1.22×10⁻⁴.

The recharge time caps the conversion rate

This is the heart of "bigger is not better." The small charge that moved in or out of C_ext during sharing must be restored to the original voltage through the source resistance R before the next sample. The time constant is τ = R·C_ext, far larger than for C_sh.

In the earlier example (R = 50kΩ, C_ext = 100nF), node gives τ = 5ms, so waiting 9τ at 12 bits takes 45ms and the sampling rate falls to about 22SPS. With no external C and the sample time set to 9τ (2.25µs), the maximum is, in theory, 444kSPS.

With a high external source resistance, a "comfortably large C" cuts the conversion rate by orders of magnitude. Choose C_ext by checking both the charge-sharing error and this recharge time.

Seen as average current: C_sh·fs acts as an input resistance

Some datasheets state the source condition as an average input impedance instead. If C_sh charges to V at every sample and this repeats fs times per second, the average current from the source is C_sh·V·fs, the same as connecting an equivalent input resistance R_eq = 1/(C_sh·fs). In node, C_sh = 5pF and fs = 1MSPS give R_eq = 200kΩ. For high-resolution, high-impedance sources, though, the 9τ settling condition is usually the tighter one.

Buffering with an op amp: a large C on the output invites oscillation

Placing an op amp voltage follower between the source and the ADC lowers the closed-loop output impedance by the loop gain, so the effective source resistance gets small. The trouble starts when you hang an external C directly on its output.

With the op amp's open-loop output resistance R_o and load capacitance C_load, the two make a new pole. For R_o = 50Ω and C_load = 0.1µF, the pole is 1/(2π·50Ω·0.1µF) ≈ 31.8kHz (node). If it falls inside the feedback loop near the unity-gain bandwidth, it cuts the phase margin sharply and causes ringing or oscillation. The root is the same as the loop gain in the op amp error article.

The standard fix is one isolation resistor of tens of Ω (for example 20 to 100Ω) between the op amp output and the capacitor (the ADC pin). Take feedback from before the resistor, the op amp output itself, and the large load C sits outside the feedback loop, so loop stability is unaffected. For how to take feedback, see the inverting, non-inverting and VCVS article.

Combining it with the anti-aliasing RC

The isolation resistor and the small C next to the ADC pin also form a first-order anti-aliasing filter. Put its cutoff well below half the sampling frequency, where it gives enough attenuation in the noise band you care about. The attenuation curve is in the RC filter attenuation article.

Do not confuse this stage's C with C_ext, the large charge-reservoir C. The C paired with the isolation resistor (tens of Ω) is driven by a low-impedance op amp output, so its time constant is small and a high fs is no problem. A large C_ext directly on the source itself (high impedance) puts a firm cap on fs through the recharge time.

実機で引っかかるところ

The reading drifts in one direction because the settling error is not random, so averaging and oversampling do not remove it. Suspect the combination of sample time and source resistance first.

Noise or offset changes with the potentiometer position because the divider's impedance changes with the wiper position. Only the first point after a multiplexer switch is wrong because C_sh still holds the previous channel's voltage; sampling the same channel twice in a row and using the second reading is a common workaround.

If adding an external C made things slower or carries old values, check whether 9τ of R·C_ext has grown longer than the sampling period.