How glass cloth affects signal quality: a PCB is not uniform

FR-4 is a woven cloth impregnated with resin

An FR-4 dielectric layer is a stack of prepreg: woven glass fiber cloth impregnated with epoxy resin. Glass (E-glass) has a relative permittivity of around 6; epoxy resin is around 3. The datasheet's "er = 4.2-4.5" is the volumetric average of the two.

The problem is that this average is not the same everywhere on the board. The cloth is woven from glass bundles (yarns) running lengthwise and crosswise; the material is thick where bundles cross and is resin alone in the gaps (windows) between them. Er is higher (slower) over a bundle and lower (faster) over a window.

The weave pitch is set by the cloth style. Common PCB styles, along with approximate pitch and thickness, are listed below.

Across all these styles, the bundle pitch runs 0.4-0.8mm. A 50 ohm trace is 0.1-0.35mm wide, and a differential pair's pitch is 0.3-0.6mm — trace geometry and weave geometry sit at almost the same scale, so whether a trace lands on a bundle or a window comes down to chance.

Speed differs by a few percent between bundle and window

The effective er directly under a trace is higher over a bundle and lower over a window. The gap depends on materials and stack-up, but for wide-window styles like 1080 or 106, an effective-er difference of 0.3-0.6 (8-15% relative to 4.0) has been reported. Since propagation delay scales with sqrt(er), the delay difference works out to 4-7% — 0.25-0.45ps/mm on a 6.5ps/mm trace.

The gap accumulates with trace length: 25-45ps over 100mm. A commonly cited rule of thumb of "10-15ps/inch worst case (0.4-0.6ps/mm)" lines up with this.

Characteristic impedance shifts for the same reason — lower over a bundle, higher over a window, by roughly ±2-4 ohm. That stays within the usual ±10% impedance tolerance, but because the variation is periodic, reflections build up at the frequency matching that period. That lands in the tens-of-GHz range, so it's negligible for ordinary digital signals.

A single trace's delay variation isn't a problem on its own — a board-to-board delay difference of tens of ps cancels out as long as the clock and data travel over the same board. What matters is a difference between two signals.

One side of a differential pair on a bundle creates skew

A differential pair runs two traces in parallel at a 0.3-0.6mm pitch, close to the cloth's 0.4-0.5mm bundle pitch. That makes it easy for one line to run the whole length over a bundle while the other runs over a window, and the delay difference between them becomes intra-pair skew.

Say that produces 30ps of skew over 100mm. At 5Gbps (200ps per bit) that's 15% — still within tolerance. At 10Gbps (100ps) it's 30%, and the eye visibly closes. At PCIe Gen4 (16GT/s, 62.5ps), it's half a bit.

Skew causes two kinds of damage: part of the differential signal converts to common mode (reducing differential amplitude at the receiver, and radiating the common-mode component as EMI), and the signal edge softens (because the two edges sum while offset from each other).

What makes this awkward is that it varies by manufacturing lot. The alignment between traces and weave depends on where the board sits on the panel, so a prototype that looks fine can turn into a hit-or-miss outcome in production.

Mitigation: don't route parallel to the weave

The basic fix is to make both lines see the same conditions, or average bundle and window within a single line. Listed in order of effectiveness:

Angle the routing. Routing at 10 degrees or more to the weave makes a single trace cross bundles and windows alternately, averaging out the effect — and both lines of a pair then see the same average. There are two ways to do this: have the whole board rotated 10-15 degrees on the panel during fabrication (fewer boards per panel, raising cost), or zig-zag the routing (uses more board area).

Use spread glass. Cloth with the bundles flattened out to eliminate the windows (spread versions of 1078, 1067, 3313, etc.; manufacturers label these MS, SI, and similar codes) reduces the location-to-location er variation. The extra cost is small, and it's becoming standard on 10Gbps-class boards.

Two thin plies instead of one thick ply. Using two plies of 1080 instead of one ply of 2116 offsets the two weave patterns from each other, averaging them out. Specify this in the stack-up as "two-ply construction for the same thickness."

Match differential pair pitch to the weave pitch. If the pair pitch equals the bundle pitch, both lines land on a bundle together (or both on a window together). This depends on the specific cloth, so it's only usable once the material and stack-up are locked in.

Low-Dk glass. Materials using a lower-er glass such as NE-glass (around 4.4) narrow the gap between glass and resin, shrinking the weave effect itself. This is used, paired with low-loss resin, at 25Gbps and above.

At what point does this start to matter

A rough guide is "bit rate times trace length." Taking skew becoming visible once it exceeds 10% of a bit period, and using a worst case of 0.5ps/mm, the allowable trace length is 0.1 x (bit period in ps) / 0.5 = (bit period in ps) x 0.2mm.

At 5Gbps (200ps), that's 40mm; at 10Gbps (100ps), 20mm; at 16GT/s (62.5ps), 12mm. Beyond these lengths, you need one of the mitigations above, or reliance on receiver-side skew compensation (built into many SerDes).

Conversely, for signals like USB 2.0 (480Mbps, 2ns), 1Gbps Ethernet, or DDR3, even 100mm only amounts to 2-5% of a bit period, and the weave effect isn't worth worrying about. Before applying a blanket rule of "route every differential pair at an angle," check whether it's actually needed at your board's signal speed.

A quick check: get the trace delay from trace length to delay, take 5% of it as a worst-case skew estimate, and compare that against the bit period.