How glass cloth affects signal quality: a PCB is not uniform

FR-4 is a woven cloth impregnated with resin

An FR-4 dielectric layer is prepreg: woven glass cloth impregnated with epoxy. Glass (E-glass) has a relative permittivity of around 6 and epoxy around 3; their volumetric average is the datasheet's "er = 4.2-4.5".

The problem is that this average is not the same everywhere on the board. The cloth is woven from glass bundles (yarns), with resin alone in the gaps (windows). Er is higher (slower) over a bundle and lower (faster) over a window. The weave pitch is set by the cloth style.

Across these styles the bundle pitch is 0.4-0.8mm. A 50 ohm trace is 0.1-0.35mm wide and a pair's pitch is 0.3-0.6mm, so trace and weave are at almost the same scale, and whether a trace lands on a bundle or a window is chance.

Speed differs by a few percent between bundle and window

The effective er under a trace is higher over a bundle and lower over a window. For wide-window styles like 1080 or 106, an effective-er difference of 0.3-0.6 (8-15% of 4.0) has been reported. Delay scales with sqrt(er), so the delay difference is 4-7%, or 0.25-0.45ps/mm at 6.5ps/mm: 25-45ps over 100mm.

Characteristic impedance shifts by roughly ±2-4 ohm. The variation is periodic, so reflections build at a matching frequency, but that is in the tens-of-GHz range and negligible for ordinary digital signals.

One trace alone is no problem: if the clock and data cross the same board, it cancels. What matters is a difference between two signals.

One side of a differential pair on a bundle creates skew

A differential pair runs two traces in parallel at a 0.3-0.6mm pitch, close to the cloth's 0.4-0.5mm bundle pitch. So one line can run the whole length over a bundle while the other runs over a window, and the delay difference becomes intra-pair skew.

Say that gives 30ps of skew over 100mm. At 5Gbps (200ps per bit) that is 15%, tolerable. At 10Gbps (100ps) it is 30% and the eye closes. At PCIe Gen4 (16GT/s, 62.5ps) it is half a bit.

Skew converts part of the differential signal to common mode (less amplitude at the receiver, plus EMI) and softens the edge.

It also varies by manufacturing lot. The alignment depends on where the board sits on the panel, so a prototype that looks fine can turn hit-or-miss in production.

Mitigation: don't route parallel to the weave

The basic fix is to make both lines see the same conditions, or to average bundle and window within each line.

Angle the routing. At 10 degrees or more to the weave, a trace crosses bundles and windows alternately and averages out, and both lines of a pair see the same average. Either have the whole board rotated 10-15 degrees on the panel (fewer boards per panel, so higher cost), or zig-zag the routing (uses more board area).

Use spread glass. Cloth with the bundles flattened to remove the windows (spread 1078, 1067, 3313, etc.) reduces the er variation. The extra cost is small, and it is becoming standard on 10Gbps-class boards.

Use two thin plies. Two plies of 1080 instead of one of 2116 offset the two weave patterns and average out.

Match pair pitch to weave pitch. If one line is on a bundle, so is the other. This depends on the cloth, so use it once the stack-up is locked in.

Low-Dk glass. NE-glass (around 4.4) narrows the glass-resin gap and shrinks the weave effect itself. It is used with low-loss resin at 25Gbps and above.

At what point does this start to matter

A rough guide is bit rate times trace length. Taking skew as visible beyond 10% of a bit period, with a worst case of 0.5ps/mm, the allowable length is (bit period in ps) × 0.2mm. That is 40mm at 5Gbps (200ps), 20mm at 10Gbps (100ps), and 12mm at 16GT/s (62.5ps). Beyond that you need a mitigation above, or receiver-side skew compensation (built into many SerDes).

Conversely, for USB 2.0 (480Mbps, 2ns), 1Gbps Ethernet, or DDR3, even 100mm is only 2-5% of a bit, and the weave effect is not worth worrying about.

Take 5% of the delay from trace length to delay as the worst-case skew.