What FPGA drive strength settings of 4mA, 8mA and 12mA actually change

"8mA" is a guaranteed current at a test point, not a limit

Choosing "8mA drive strength" is often misread as limiting the pin to 8mA. It is the opposite: it guarantees at least this much current at the VOL/VOH voltage test point. In JEDEC JESD8-B too, IOL is a condition for guaranteeing VOL, not a ceiling.

The output stage is push-pull MOSFETs (of different gate widths or counts) in parallel, and the strength setting switches how many are on at once. More devices lower the parallel resistance, so the larger the catalog "xx mA", the lower the output resistance.

The current that actually flows is only what the load demands, and strength changes output impedance and slew rate.

Output resistance by strength

Output resistance can be estimated by dividing VOL (or VDD − VOH) by the current IOL guaranteed at that strength: R_out ≈ V_OL ÷ I_OL. Here it is calculated for LVCMOS33 with a VOL spec of 0.4V.

This is a back-calculation from the VOL test point, close to but not equal to the actual small-signal output resistance (the slope of the IBIS V-I curve). When you need accuracy, read the Pulldown/Pullup tables of the IBIS model directly, as described in "Reading a driver's output resistance and rise time from an IBIS file".

Too strong: ringing and overshoot

If the output resistance is below the trace impedance Z₀ (50Ω is common on boards) and the far end is open (a high-impedance input), the wave reflects again at the receiver and the voltage jumps.

The voltage right after the launch is V_launch = VDD × Z₀ ÷ (Z₀ + R_out), and the first peak at the open far end approaches twice that. For VDD = 3.3V and Z₀ = 50Ω, 16mA (R_out ≈ 25Ω) reaches about 4.4V and 12mA (33Ω) reaches 3.98V, while 8mA (50Ω, nearly matched) stays at VDD, 3.3V.

The absolute maximum rating of a 3.3V IC is often 3.6V, and both 4.4V and 3.98V exceed it. Besides overshoot, there is long-term degradation from repeated current through the receiver's protection diodes, and double clocking or miscounts when the waveform crosses the threshold several times. The conditions under which a trace acts as a transmission line are covered in How long a trace must be to become a transmission line.

Too strong: simultaneous switching noise (SSN)

The other effect appears when several outputs switch at the same time. Between the GND pin and the die GND there is parasitic inductance L_gnd from bond wires, package routing and BGA vias. When N outputs switch together their di/dt adds up, and the die-side GND reference jumps by V = L_gnd × (dI_total/dt). This is ground bounce, the main cause of SSN (simultaneous switching noise).

Drive 16 loads of 10pF high at once with a 1ns rise time. The charging current is I = C·V/t = 10pF × 3.3V ÷ 1ns ≈ 33mA per output, about 528mA for 16. With a BGA package GND inductance of 1nH, the bounce is V = 1nH × 528mA ÷ 1ns ≈ 0.53V. Through QFP bond wires (L_gnd ≈ 4nH), the same conditions give about 2.1V.

The die's internal GND itself rises, so other inputs that are still logic L appear to swing toward H relative to it, and a static signal on the same bank can be read wrongly.

Too strong: EMI and supply current

Faster edges widen the bandwidth. By the rule of thumb BW ≈ 0.35 ÷ t_r, content extends to about 350MHz at t_r = 1ns and about 700MHz at 0.5ns. This is the range that tends to cause trouble in radiated-EMI testing, and raising the strength pushes emission toward higher frequencies.

Average power (P = C·V²·f) does not depend on strength, but the peak current grows as output resistance falls, which makes the decoupling ESR and mounting inductance requirements harder. The effect of via inductance is in Via inductance blunts decoupling.

Too weak: delayed rise into a capacitive load

With high output resistance, the time constant τ = R_out × C for charging trace and input capacitance (a few pF to tens of pF together) grows. With 4mA (R_out ≈ 100Ω) into 20pF, τ = 2ns and the 10-90% rise time is about 2.2 times that, around 4.4ns. At 12mA (33Ω), τ is about 0.66ns and the rise shrinks to just under 1.5ns.

This delay goes straight into the setup/hold calculation. A bus where only one pin has a different strength setting can lose margin on that pin, which happens often. Rise-time calculations for each load capacitance are in Trace capacitance and whether the driver can drive it.

The trap of combining with a damping resistor: overdamping

The standard way to match a trace is a series (damping) resistor of 22Ω or 33Ω at the source so that R_out + R_s ≈ Z₀. But R_out changes with drive strength.

8mA (R_out ≈ 50Ω) is already nearly matched to a 50Ω trace. Adding 33Ω makes the total 83Ω, and the launch voltage is only VDD × 50 ÷ (50 + 83) ≈ 1.24V; the waveform is overdamped, rising in steps toward VDD after another round trip of reflection. You raise the strength to go faster, and adding the damping resistor by habit makes it slower.

Adding 33Ω to 16mA (R_out ≈ 25Ω) gives 58Ω, close to Z₀ = 50Ω, which is how a damping resistor is meant to be used. Choose its value after fixing the strength, by looking up the R_out estimate, rather than using 22Ω or 33Ω as a fixed value.

How this differs from the slew rate setting (SLOW/FAST)

FPGA I/O attributes also include a SLOW/FAST slew rate setting, separate from drive strength. Strength sets the output resistance (the static current drive), whereas slew rate changes only the rise time t_r at the same output resistance, by current-limiting the output stage's drive to slow the gate charge.

Its effect on SSN is squared. Current I = C·V/t_r and its rate of change dI/dt both fall as t_r grows, so bounce voltage scales roughly as 1/t_r². For the 16-output, 10pF, L_gnd = 1nH case above, FAST (t_r = 0.5ns) gives about 2.1V and SLOW (t_r = 2ns) about 0.13V. When you want a little more speed without raising strength, moving the slew rate from SLOW to FAST can speed things up with less SSN impact than raising strength. Conversely, if SSN is the problem, suspect SLOW first.

Steps for choosing

1. Check the trace characteristic impedance Z₀ from the stackup (45-55Ω is common for microstrip).
2. Find the load capacitance (trace plus receiver input) and the upper limit on rise time worked back from timing constraints, then pick the smallest strength that meets it.
3. Find R_out, and decide whether a damping resistor is needed and its value from R_out + R_s ≈ Z₀.
4. Count the pins that switch simultaneously. If SSN is severe, lower the strength, use SLOW, add GND pins, or stagger the switching.
5. Confirm on the bench with an oscilloscope, checking both overshoot at the receiver and false toggling on neighboring pins (SSN), before finalizing.