How tight does length matching need to be?

1mm is 6–7ps

On FR-4, signal propagation delay runs 6–6.5ps/mm on microstrip (an outer layer) and around 7ps/mm on stripline (an inner layer). An outer layer sees air on one side, which lowers its effective dielectric constant and speeds the signal up.

The point of length matching is to align the arrival times of several signals. The tolerance you actually need is derived backward from that signal group's timing margin. A 100ps margin allows a 15mm length difference; a 10ps margin allows 1.5mm.

So before you start matching lengths, you need to know the timing margin, in ps, for that signal group. Matching everything to 0.1mm without knowing that number is just spending time routing — it is not design.

Signals that need it, and signals that do not

SPI, I²C, UART, and low-speed parallel buses. A 20MHz SPI has a 50ns period, with several ns or more of setup/hold margin. Even a 100mm length difference is only 650ps — under a fifth of that margin. Length matching is unnecessary, and adding serpentines to pad the length out does more harm than good.

Source-synchronous buses (DDR, high-speed parallel ADCs, and the like). Data travels alongside a clock or strobe, and the receiver latches data on that strobe. A DDR3-1600 bit is 625ps wide, and fitting setup and hold inside that leaves only tens of ps of margin between data and strobe. Within a byte lane (DQ0–7 and DQS) you need roughly ±0.5–1mm. Address, command, and clock are looser, at a few mm. The exact numbers come from the memory controller vendor's design guide — follow those.

Differential pairs. A length difference between the two lines of a pair (intra-pair skew) converts part of the signal from differential to common mode. Aim for about 1mm with USB 2.0 High Speed (480Mbps, a 2.08ns bit), and 0.1–0.3mm at the multi-Gbps rates of USB 3.x or PCIe. The length difference between pairs (inter-pair skew) is often absorbed by the protocol, so the requirement is looser.

Clock distribution. When the same clock feeds several ICs, differences in arrival time at each IC eat into the margin for passing data between them. For a synchronous bus running off one clock, the margin is typically some fraction of the period — at 100MHz (a 10ns period) that is often around 1ns, or 150mm.

Matching length does not guarantee matching delay

The tool you have is length, but what you actually want to equalize is delay. Several things can leave delay mismatched even when length is identical.

Speed differs by layer. Outer layer (6ps/mm) and inner layer (7ps/mm) differ by 15%. A 100mm trace routed half on an inner layer versus one routed entirely on an outer layer ends up 25ps apart even at equal length. Route a signal group on the same layer throughout, or convert the per-layer delay difference into an equivalent length and match that instead.

Vias. A via is a vertical run equal to the board thickness — around 10ps for a 1.6mm board. Either match the number of vias, or treat each via as an equivalent 1.5–2mm of trace.

Coupling in serpentine routing. Folding a trace back on itself to add length couples the adjacent runs together, so the signal takes a shortcut and ends up with less delay than intended. Keep the spacing between folds at 3–4x the trace width or more, and prefer a few large folds over many short ones.

Package-internal routing. Between a BGA ball and the pad on the die there is a few mm to over ten mm of routing inside the package, and it differs pin to pin. DDR controller and FPGA vendors publish a "package delay table" for exactly this — add it to the board trace length before matching. It is entirely normal to be chasing 1mm precision on the board while the package itself is 5mm off.

Procedure

1. Read the length-matching requirement (in mm or ps) for each signal group from the device's design guide. If it is not stated, derive it backward from the timing margin.
2. Route each signal group on the same layer stack-up — the same outer/inner choice and the same via count.
3. Fix the longest trace first and stretch the others to match it. You cannot match by shortening, so do not let the longest trace run any longer than it needs to.
4. Where package delay applies, enter it into the CAD tool or correct each pin's target length by hand.
5. Keep serpentine spacing at 3W or more. Place the folds near where the length difference actually arose, not at the receiving end of the signal.
6. If you do not know the margin for a signal, do not match it. Matching costs routing area and time; matching a signal that did not need it gains nothing.