Reading a driver's output resistance and rise time from an IBIS file

What is in an IBIS file: Component, Pin, Model

IBIS (I/O Buffer Information Specification) is a standard that hands over a driver's output stage as text: V-I tables and rise-time tables instead of a SPICE model. A datasheet's "output resistance about 10Ω" or "rise time 1ns" is a single typical value, but an IBIS file almost always carries tables for all three typ/min/max corners, so you can follow the process spread to its ends.

The numbers here come from demo_cmos33.ibs, loaded with "Try the demo model" in the IBIS waveform simulator (a synthetic 3.3V CMOS model, not a real device).

Under [Component] are [Package] and [Pin]. [Package] holds the parasitics from board land to die in three typ/min/max sets; in demo_cmos33.ibs they are R_pkg = 0.060Ω, L_pkg = 2.50nH and C_pkg = 0.35pF (typ). [Pin] lists signal_name, model_name and R_pin/L_pin/C_pin for each pin, so it is the map from pins to [Model]s.

Inside [Model] are the V-I tables you want ([Pulldown]/[Pullup]/[GND_Clamp]/[POWER_Clamp]) and the rise-time data ([Ramp], or [Rising Waveform]/[Falling Waveform] in some models). An Input model has only Vinh/Vinl thresholds, while Output and I/O models carry the driver characteristics.

What typ/min/max mean, and the Pullup trap

typ/min/max are not resistor tolerances but three operating corners combining process, supply voltage and temperature. The min column is a weak, slow driver with less current and the max column a strong, fast driver with more current, and this pairing holds across [Pulldown], [Pullup], [Ramp] and [GND_Clamp] in the same file.

The voltage axis is easy to misread. [Pulldown] and [GND_Clamp] voltages are the pin voltage itself (GND-referenced), but [Pullup] and [POWER_Clamp] voltages are written as Vcc − V(pin). This format lets the same table shape serve different supply voltages, but reading "I = −62mA at V(pin) = 1.0V" literally gets both sign and value wrong. The simulator on this site also evaluates the Pullup current as I(Vcc − V(pin)).

In demo_cmos33.ibs, the [Pullup] of DEMO_OUT_33 has I(typ) = −61.96mA on the row with table voltage 1.0V. With Vcc = 3.3V, that means the pin sources 61.96mA at a pin voltage of 2.3V.

Reading Ro from the V-I tables

Read Ro from the slope of the tangent near the origin of the V-I table. Do not pick one point and compute V ÷ I: [Pulldown] is a nonlinear curve, with the FET in its linear region acting like a resistor at low voltage and saturating, so current grows more slowly, as voltage rises.

Check it on the DEMO_OUT_33 [Pulldown] typ column. At V = 0.1V, I = 9.09mA, so Ro ≈ 0.1V ÷ 9.09mA ≈ 11.0Ω, the small-signal Ro. At V = 3.3V in the same table, I = 123.1mA and V ÷ I is 26.8Ω. The same table shows Ro 2.4x apart depending on where you read it because of the nonlinearity, and only the slope near the origin deserves the name Ro. To estimate the voltage drop at large swing, interpolate the table itself.

Taking the slope near the origin in the min and max columns gives Ro_min (weak, slow corner) ≈ 13.7Ω and Ro_max (strong, fast corner) ≈ 9.0Ω. The same pin changes Ro by 1.5x across corners.

The [Pullup] side works the same way: draw the tangent near Vcc (table voltage near 0V). In the DEMO_OUT_33 [Pullup] typ column, table V = 0.1V (pin voltage 3.2V) gives I = −7.15mA, so Ro_typ ≈ 14.0Ω. That is larger than the Pulldown 11.0Ω, so this driver is asymmetric, with a different Ro for H and L. That is why the best damping resistor can differ between H and L outputs. For a strict design, calculate Rs from each side's Ro and match the side where the harm is greater (usually the faster edge).

Reading rise time from [Ramp]

[Ramp] holds dV/dt_r (rising) and dV/dt_f (falling) as "voltage change / time" for each of typ/min/max. The interval is defined as 20% to 80% of the swing, so dt can be used directly as the 20-80% rise time t_r (the 0-100% full-swing time is roughly t_r ÷ 0.6). The R_load in the test conditions (often 50Ω) is a reference load for measurement, not your trace impedance.

The DEMO_OUT_33 [Ramp] is dV/dt_r = 0.980/1.05E-9 (typ), 0.720/1.85E-9 (min), 1.180/0.72E-9 (max). Reading dt gives 1.05ns for typ, 1.85ns for the weak, slow corner (min column) and 0.72ns for the strong, fast corner (max column). The strong corner with small Ro in Pulldown also has the fast edge in Ramp, so the corner pairing is consistent across tables.

From rise time to critical trace length

Whether a trace behaves as a transmission line follows the critical length ℓ = t_r ÷ (6 × t_pd) from How long a trace must be to become a transmission line. Substituting t_r from [Ramp] gives the critical length specific to that IBIS model.

As the table shows, the critical length of the same pin moves 2.6x with the corner, from 18mm to 47mm. Size the trace to the fastest corner's 18mm, not typ's 27mm. A trace that cannot stay within 18mm needs reflection control (termination or a damping resistor).

Choosing the damping resistor Rs = Z0 − Ro

If the trace exceeds the critical length, the simplest fix is series termination at the source (a damping resistor). Choose Rs = Z0 − Ro so that Rs plus Ro equals the characteristic impedance Z0. With Z0 = 50Ω and Ro_typ = 11.0Ω, Rs = 39.0Ω, and the E96 value 39.2Ω can be used as is.

The problem is that Ro ranges from 9.0 to 13.7Ω across corners while the mounted Rs is a fixed value. Choosing Rs = 39Ω on the typ basis gives Rs + Ro = 48.0Ω < Z0 at the strong, fast corner (Ro = 9.0Ω): the reflection at the receiver (a nearly open input) takes the voltage about 2% above the final value, and that reflection reflects again at the source and remains as small ringing. At the weak, slow corner (Ro = 13.7Ω), Rs + Ro = 52.7Ω > Z0, the first step reaches only about 97% of the final value, and the waveform is overdamped, converging on the second step.

If noise immunity comes first, choose Rs so that Rs + Ro ≥ Z0 even at the corner with the smallest Ro. Here Rs = Z0 − Ro_max = 50 − 9.0 = 41Ω, and no corner overshoots. The staircase (overdamping) at the weak, slow corner gets a little deeper, but it does less harm than ringing in most cases.

What Ro and timing alone do not tell you

• C_comp: the [Model] C_comp (typ 3.00pF for DEMO_OUT_33) is the die capacitance. Unless you add it to the trace and connector capacitance, the real edge is slower than the Ramp table says.
• Package L_pkg: the [Package] L_pkg (typ 2.50nH) matters more the faster the current changes. Assuming the Pulldown current goes from 0 to 123mA in 1.05ns at the typ corner, V = L × dI/dt ≈ 2.5nH × (0.123A ÷ 1.05ns) ≈ 0.29V. That is about 9% of a 3.3V swing and one cause of overshoot and ringing that an Ro-only model cannot explain.
• [Ramp] R_load: the Ramp dV/dt was measured into R_load (often 50Ω). If your trace Z0 differs a lot (25Ω or 100Ω, say), the rise time shifts somewhat from the table. A strict answer needs a transient analysis including the V-I tables, C_comp and the package RLC, which is what the simulator does.