Delay difference between outer microstrip and inner stripline: why length-matched traces still shift DDR timing

The same 50mm differs by 71ps between outer and inner layers

Route the same 50mm on FR-4 (εr = 4.3), once as outer-layer microstrip and once as inner-layer stripline, and the outer layer takes 274.7ps and the inner layer 345.8ps. The 71.2ps difference is 23% of one unit interval (UI, the data-capture window) of DDR4-3200, 312.5ps. The "length" a length-matching tool shows is a physical distance, not the time the signal arrives.

Figure 1: outer-layer microstrip (left) leaks part of its field into air, lowering the effective permittivity. Inner-layer stripline (right) is surrounded by board material above and below, so the whole field stays in the board.

Why the effective permittivity differs

An outer-layer trace (microstrip) is asymmetric: a ground plane below, air above and beside. The field extends not only under the trace but also out the sides and up, into air (fringe field). Air has a relative permittivity of 1, far below the board material (about 4.0-4.4 for FR-4), so the effective permittivity εeff that the signal sees is lower than εr.

The approximation used here is the IPC-2141 formula, the same as in the microstrip impedance calculator: εeff (outer) = 0.475 × εr + 0.67. For εr = 4.3 that gives εeff = 2.713, about 37% below εr.

An inner-layer trace (stripline) sits between ground or power planes, surrounded entirely by the same board material. For a symmetric stripline the field passes through the same permittivity in every direction, so εeff equals the board's εr.

Propagation velocity is v = c / √εeff and delay is td = √εeff / c (c is the speed of light, 0.2998mm/ps; the same formula as the propagation speed calculator). The lower the εeff, the faster the signal, so the outer layer is faster than the inner layer.

The difference per millimeter

FR-4's εr scatters over about 4.0-4.4 with the lot and measurement frequency, so calculate across that range.

Propagation delay of outer layer (microstrip) and inner layer (stripline). εeff (outer) = 0.475εr + 0.67, εeff (inner) = εr, td = √εeff / 0.2998 ps/mm
εr	Outer (ps/mm)	Inner (ps/mm)	Difference (ps/mm)	Difference over 50mm	Ratio to 1 UI (312.5ps)
4.0	5.35	6.67	1.32	66.2ps	21.2%
4.2	5.45	6.84	1.39	69.5ps	22.3%
4.4	5.54	7.00	1.46	72.8ps	23.3%

With εr from 4.0 to 4.4, the difference stays at 1.3-1.5ps per mm, 66-73ps over 50mm. The choice of outer or inner layer matters more than the spread in εr.

How big is it against one UI of DDR4-3200

DDR4-3200 runs at 3200MT/s, so 1 UI = 1 / 3200MHz = 312.5ps. The memory captures DQ against DQS (the data strobe), so the DQ-DQS skew as a share of the UI directly eats timing margin.

Route DQ on the outer layer and DQS on the inner layer (or the reverse), each 50mm, and the 71.2ps skew alone uses 22.8% of the UI. For DDR5-6400 (1 UI = 156.25ps) it is 45.6%.

The rule is to keep one byte (DQ group) on one layer, but BGA congestion can still push part of the DQ group to another layer, or add extra vias on DQS alone.

Figure 2: two 50mm traces, one outer and one inner, launched together. The outer-layer pulse arrives first and the inner-layer pulse 71.2ps later.

Add the vias too

Changing layers always goes through a via. A via's delay, as the vertical travel through dielectric, is approximated with the same √εr/c formula as the inner layer. For a 1.6mm board with εr = 4.3 it is about 11.1ps per via, a bit over 22ps for the down-and-up pair.

Take DQ and DQS routed differently on a 1.6mm board. DQ is 6mm outer + 42mm inner (48mm total), DQS is 30mm outer + 16mm inner (46mm total), and both pass through two vias (the length difference is 2mm).

DQ is 6mm outer (33.0ps) + 42mm inner (290.5ps) + two vias (22.1ps) = 345.6ps. DQS is 30mm outer (164.8ps) + 16mm inner (110.7ps) + two vias (22.1ps) = 297.6ps. The difference is 48.0ps, 15.4% of a UI, far more than the 2mm length difference suggests. A length DRC does not show it.

A via that is not back-drilled keeps a stub, an unused copper barrel extending below the section the signal uses. A stub matters more for reflection and impedance discontinuity than for delay, but some EDA tools count the full via length, stub included, so the delay calculation shifts with back-drilling. When comparing paths, check how stubs are treated.

Figure 3: DQ routed mostly inner (6mm outer + 42mm inner), DQS mostly outer (30mm outer + 16mm inner). The length differs by 2mm, but the delay differs by 48ps (15.4% of a UI).

What "match by time" does in EDA

Most PCB CAD length-matching tools match physical length by default. That is enough if each byte always stays on one layer. With layer changes, switch to matching by time (a feature called Delay Tuning, Phase Tuning, and so on).

That feature gets a per-layer delay coefficient (ps/mm) from the effective permittivity or impedance setting, multiplies it by each segment's length, sums them, and adds the delay of the vias. The principle is the same as this article's calculation, except that it is automatic and uses coefficients calculated from the stackup.

Matching by time means the lengths no longer match. With a 50.0mm outer-layer DQ, an inner-layer DQS needs 39.7mm, 10.3mm shorter, to reach the same 274.7ps. The inner layer is slower per mm, so matching time means cutting length. The picture "equal length" suggests is sometimes the opposite of what the tool does.

Figure 4: left, matching length passes the DRC but the delays differ by 71ps. Right, matching delay makes the inner-layer DQS 10.3mm shorter than the outer-layer DQ.

Solder resist and dispersion

Solder resist (εr ≈ 3.3-4.0, depending on the product) covers outer-layer traces and fills part of what was air. The medium the fringe field passes through has a higher permittivity, so the effective permittivity is slightly higher than the no-resist calculation, and outer-layer delay moves up by a few percent. The increase depends on width, thickness and resist thickness, so the values here are an approximation without resist. For tight timing, correct with a field-solver calculation or a measurement.

This article's calculations use εr at low frequency (the datasheet conditions, often 1MHz or 1GHz). A board material's εr tends to fall as frequency rises (dielectric dispersion), so for fast-edge signals like DDR4-3200, delays from the datasheet εr may be slightly longer than reality. The effect on the outer-inner difference is relatively small since both layers shift the same way, but to match absolute delay to the ns, ask the board maker for εr over the band in use (Df/Dk). Local variation from the glass weave is a separate factor, covered in how glass weave affects signal quality.

Where it goes wrong on real boards

The DRC passes, but memory training fails only at certain temperature and voltage corners. Layer skew shows up only under conditions where it stacks with other factors (supply noise, crosstalk).
Read leveling or write leveling passes on some lots and fails on others. The board maker's εr tolerance (typically about ±10%) bites at a marginal design.
On an oscilloscope, the DQ and DQS edges overlaid differ by tens of ps from board to board. If the offset changes with a revision that changed the stackup, suspect layer-related skew.
An SI analysis tool reports "lengths match but it is slow." Timing reports look at time, so check that warning separately from the DRC.

Frequently asked questions

If I keep every trace on just the outer (or inner) layer, does this problem go away?

Yes. In practice, though, ground return, crosstalk and routing congestion often stop you from routing the whole group on one layer. If keeping to one layer would split a ground plane or disturb the return path, changing layers and matching by time can be safer.

If I match the via count, do I only need to watch the length?

No. Even with equal via counts, delays differ if the outer and inner shares differ. In the example here (DQ 48mm, DQS 46mm, two vias each) the difference is still 48ps. What to match is neither via count nor length but the time, summed segment by segment.

Can I use the εr in the board maker's datasheet as is?

As a guide, yes. But the datasheet εr is at a specific frequency (such as 1MHz) and falls somewhat over the real signal band, and lots differ by about ±5-10%. The outer-inner difference barely depends on εr, so datasheet values are fine for a rough estimate. Do final verification with a field solver using the maker's stackup.

Does this apply to differential pairs (DQS is routed as a pair)?

Yes. A differential pair also has a different effective permittivity on outer and inner layers, so its velocity differs. Manage intra-pair skew separately; the skew from layer differences against DQ follows this article directly.

Does DDR5 make this worse?

Yes. The DDR5-6400 UI is 156.25ps, half of DDR4-3200 (312.5ps). The 71.2ps skew here (εr = 4.3, 50mm, split across outer and inner layers) is 22.8% of a UI for DDR4 and 45.6% for DDR5.

Standards and references

IPC-2141B, PCB特性インピーダンスと伝搬遅延の計算 — Approximation with microstrip effective permittivity εeff = 0.475εr + 0.67 and stripline εeff = εr
JEDEC JESD79-4, DDR4 SDRAM 規格 — Definition of data rate and UI (1 UI = 1/data rate), and DQ/DQS timing parameters
E. Bogatin, "Signal and Power Integrity - Simplified" — Effective permittivity of outer and inner layers, delay change from solder resist, and dielectric dispersion
各社PCB CADのマニュアル(Delay Tuning / Phase Tuning / Layer-aware length matching) — Adding per-layer delay coefficients and via delay to match by time instead of physical length