Microstrip trace width is decided by the stack-up

What sets the width is the dielectric under the trace

A microstrip is a top-layer trace paired with the GND plane directly beneath it. Four things fix its characteristic impedance: trace width w, trace thickness t, dielectric thickness to the plane h, and the dielectric constant εr.

Only w is the designer's to choose. t comes from the copper weight (roughly 35 µm for 1 oz, 40–50 µm after plating), and h and εr come from the stack-up. For the same 50 ohms, w is about 0.35 mm at h = 0.2 mm and about 0.15 mm at h = 0.1 mm: halve h and the required width halves with it.

Fix the width first and change the stack-up afterward, and the impedance will be well off target. Decide the top-to-layer-2 spacing first.

What a "standard" 4-layer, 1.6 mm build actually gives you

A four-layer, 1.6mm overall thickness does not specify the top-to-L2 dielectric thickness. This comparison assumes h = 0.2mm and 0.1mm. Obtain the fabricator's finished dielectric/copper thicknesses, material and frequency conditions; a glass-cloth style name alone does not fix the pressed thickness.

The chart compares an illustrative 50Ω width of about 0.35mm at h = 0.2mm. Escape feasibility depends on pad width, clearance, vias and fabrication rules as well as pitch. Check the recommended land pattern and fabrication rules, including a short narrow escape before widening where appropriate.

Thin the top dielectric and the width shrinks to 0.1 mm range

Thin the top-to-layer-2 dielectric to 0.1 mm or below and the 50 ohm width drops to 0.15 mm or less, which breaks out from fine-pitch parts. The trade-off is a thicker inner dielectric to keep the board at 1.6 mm. Some fabs offer an "impedance-ready 4-layer" as standard; specify that from the start.

The chart uses rounded IPC-2141 approximation examples with 35µm copper and εr ≈ 4.3. It omits solder mask and adjacent copper. Agreement within a few percent between an approximation, field solver and fabricator is not guaranteed; agree the fabrication width using the actual stack-up and calculation method.

How far manufacturing variation moves the impedance

A board designed for 50 ohms will not come back at exactly 50 ohms. Three things mainly move it.

Dielectric thickness. Prepreg resin flows under heat and pressure, so thickness varies about ±10% from nominal. ±0.01 mm on h = 0.1 mm is roughly ±2–3 ohms.

Trace width. Etching adds an error of around ±0.02 mm toward a narrower trace: 13% of a 0.15 mm trace, or roughly ±3 ohms.

Dielectric constant. FR-4's εr spans roughly 4.0–4.7 depending on material, glass content, and frequency; ±0.2 is worth about ±1 ohm. εr falls as frequency rises (around 4.2 at 1 GHz, 4.0 at 10 GHz).

The figure's 45–55Ω range is illustrative, not a guaranteed range for an uncontrolled board. Evaluate the fabricator's thickness, width and material tolerances. For impedance control, agree the tolerance, coupon location, measurement method, acceptance criteria and permitted width changes.

The solder-mask effect depends on thickness, material and geometry. The illustrated −2–3Ω is an example, not a universal correction to subtract; model the actual cross-section.

Tell the fab an impedance, not a width

For an impedance-control request, hand over a target impedance, not the width as an absolute figure. The fab fine-tunes the width for its own process, so a trace drawn at 0.15 mm may come back at 0.16 mm.

The request should give the net, the target impedance and tolerance (e.g. 50Ω ±10%, differential 100Ω ±10%), the design width and gap, and the layer and reference-plane layer. Take the fab's proposed stack-up and have them return a stack-up drawing with dielectric thicknesses and material names; without it, the next revision cannot reproduce the result. If the fab changes the width the gap moves too, so leave margin to neighboring traces.

Also check the reference plane is not broken (impedance spikes over a slot or large cutout), the width does not neck down mid-run (fine if a few mm or less; a long section is a discontinuity), and the reference plane does not change across a via (the return path breaks).

When to hand-calculate and when to use the tool

Use the characteristic impedance calculator to compare how width changes with dielectric thickness and εr. Its approximation is not a manufacturing guarantee; check the final result against the agreed cross-section, materials and tolerances.

Above a few GHz, with loss, solder mask, and copper roughness in play, you are in field-solver and low-loss-material (Megtron, Rogers, etc.) territory.