Microstrip trace width is decided by the stack-up

What sets the width is the dielectric under the trace

A microstrip is a top-layer trace paired with the GND plane directly beneath it. Four things fix its characteristic impedance: trace width w, trace thickness t, dielectric thickness to the plane h, and the dielectric constant εr.

Of these, only w is really the designer's to choose. t comes from the copper weight (roughly 35 µm for 1 oz, 40–50 µm after plating), and h and εr come from the stack-up. For the same 50 ohms, w works out to about 0.35 mm at h = 0.2 mm, about 0.15 mm at h = 0.1 mm, and about 0.1 mm at h = 0.075 mm. Halve h and the required width halves with it.

So before the trace width can be set, you need to know "how many mm sit between the top layer and layer 2 on this board." Fix the width first and change the stack-up afterward, and the impedance will be well off target.

What a "standard" 4-layer, 1.6 mm build actually gives you

Tell a fab only "4-layer, 1.6 mm" and you will usually get a build where the top-to-layer-2 dielectric is around 0.2 mm. That is because a core (1.0–1.2 mm) sits in the middle with one or two sheets of prepreg laminated on each side under the outer copper. Prepreg thicknesses run roughly 0.07 mm for 1080, 0.11 mm for 2116, and 0.19 mm for 7628, and which sheets get used is up to the fab's stock and process.

Hitting 50 ohms in that build calls for a width around 0.35 mm; a 100 ohm differential pair needs roughly 0.2 mm width with a 0.2 mm gap. You cannot break out a 0.35 mm trace from a 0.5 mm-pitch QFP or a 0.8 mm-pitch BGA, so boards carrying high-speed signals often cannot use the "standard" build as-is.

Thin the top-to-layer-2 dielectric to 0.1 mm or below and the 50 ohm width drops to 0.15 mm or less, which breaks out cleanly from fine-pitch parts. The trade-off is a thicker inner dielectric to keep the overall board at 1.6 mm. Many fabs keep an "impedance-ready 4-layer" as a standard offering, and specifying that from the start is the quicker path.

The approximation and a fab's field-solver result typically differ by a few percent. Use the approximation to get in the right neighborhood, then let the fab's own calculation set the final width.

How far manufacturing variation moves the impedance

A board designed for 50 ohms will not come back at exactly 50 ohms. Three things mainly move it.

Dielectric thickness. Prepreg resin flows under heat and pressure, so thickness typically varies about ±10% from nominal. A ±0.01 mm swing on h = 0.1 mm moves the impedance by roughly ±2–3 ohms.

Trace width. Etching tends to undercut the design value by around ±0.02 mm. On a 0.15 mm trace that is 13%, worth roughly ±3 ohms — and the effect grows as traces get narrower.

Dielectric constant. FR-4's εr spans roughly 4.0–4.7 depending on the material, glass content, and frequency; a ±0.2 swing is worth about ±1 ohm. εr falls as frequency rises (around 4.2 at 1 GHz, around 4.0 at 10 GHz), so it is worth checking which frequency a given number was calculated at.

Add these up and a 50 ohm trace built without any impedance control should be assumed to land anywhere from 45 to 55 ohms. Ask a fab for impedance control and they will measure a test coupon, adjust the width and prepreg, and guarantee ±10% (±5 ohms); some fabs will hold ±7% or ±5% for extra cost.

Solder mask matters too. A soldermask (εr≈3.5–4) over the top-layer trace drops the impedance by 2–3 ohms. A fab's own calculation already accounts for the mask, so if you run the approximation yourself, remember to subtract a few ohms from the bare-copper figure.

Tell the fab an impedance, not a width

The rule for an impedance-control request is to hand over a target impedance, not the design width as an absolute figure. The fab will fine-tune the width for its own materials and process, so a trace you drew at 0.15 mm may come back at 0.16 mm.

The request should specify:

the net in question (signal name, or layer and class), the target impedance and tolerance (e.g. 50Ω ±10%, differential 100Ω ±10%), the width and gap used in the design, and the layer and reference-plane layer involved. Take the stack-up the fab proposes and have them return a stack-up drawing that states the dielectric thicknesses and material names. Without that drawing, the next revision cannot reproduce the result.

For differential pairs, routing both members on the same layer, holding a constant gap, and locking width and gap in the CAD design rules are all assumed. If the fab adjusts the width, the gap usually moves with it, so leave margin in the clearance to neighboring traces.

• Check the reference plane is not broken. A trace crossing a slot or a large cutout in the plane sees a local impedance spike right there, which defeats the point of having the impedance controlled at all.
• Check the width is not changing mid-run. Necking down the width just under a fine-pitch part is fine if it is short (a few mm or less), but a long necked-down section becomes a discontinuity.
• Check the reference plane does not change across a via. Moving from the top layer to an inner layer can switch which GND you are referenced to, breaking the return path. Place a GND via nearby.

When to hand-calculate and when to use the tool

Our characteristic impedance calculator is meant for getting a width estimate from a stack-up. It runs on an approximation, so expect a few percent of error for narrow traces (w/h below 1) or thick copper.

That accuracy is enough as long as the fab sets the final value. What matters more is a feel for how much the width moves when the stack-up changes and how far variation can push the result off target — so run the numbers a few times sweeping h and εr to build that intuition.

A field solver becomes necessary once you need loss included above a few GHz, or need to see the effect of solder mask and copper roughness. Designs needing that level of accuracy are usually also the point where you'd consider a low-loss material (Megtron, Rogers, etc.) instead of FR-4.