Trace capacitance, and whether the driver can charge it

A trace runs about 1pF per centimeter

The per-length capacitance of a trace over a plane comes from the characteristic impedance Z0 and propagation delay t_pd: C = t_pd / Z0. For a 50 ohm microstrip (6.5ps/mm), that's 0.13pF/mm, or 1.3pF per cm. A stripline on an inner layer (7ps/mm) gives 1.4pF/cm. A narrow, high-impedance trace far from the plane (100 ohm) is about half that, 0.65pF/cm.

What the trace connects to adds further capacitance. A CMOS input pin is 3-10pF, an ESD protection diode is 1 to several pF (0.2-0.5pF for a low-capacitance part meant for high-speed signals), a connector pin is 1-3pF, and a single via is 0.3-0.5pF.

For example, a 10cm trace feeding three receiver ICs (5pF each), one ESD protection device (3pF), and one connector (2pF) adds up to 13 + 15 + 3 + 2 = 33pF. Extend it another 30cm between boards with a flat cable (50-100pF/m) and that adds 15-30pF more, landing at 50-60pF.

Time to charge it

With driver output current I and load capacitance C, raising the voltage by delta-V takes t = C x delta-V / I. With C = 50pF, delta-V = 3.3V, I = 8mA, that's 20ns. Since the datasheet's I_OH/I_OL figures (4mA, 8mA, 12mA, etc.) are the guaranteed current at the specified V_OH/V_OL, this calculation is a conservative estimate.

A closer approximation treats the output as a resistance R_on charging an RC. With V_OL = 0.4V at I_OL = 8mA, R_on ≈ 50 ohm. tau = 50 ohm x 50pF = 2.5ns, and the 10%-90% rise time is 2.2 x tau = 5.5ns. Add the IC's own internal delay and that's the rise time seen at the receiver.

A 20MHz clock has a 50ns period, split 25ns high and 25ns low. If rise and fall each take 5-6ns, that alone eats a fifth of the period in transitions and skews the duty cycle. At 50MHz (a 10ns half-period) it no longer works at all. On a trace with a large load capacitance, drive strength sets the frequency ceiling.

On a microcontroller or FPGA with selectable drive strength, choose the lowest setting that meets the load requirement. A stronger setting gives faster edges, but also more ringing, crosstalk, and radiated noise.

Power is C x V^2 x f

Charging a capacitor to V dissipates 1/2·CV^2 as heat in the driver's resistance, and discharging it dissipates another 1/2·CV^2. That's CV^2 per cycle, so toggling at frequency f gives P = C x V^2 x f. 50pF x 3.3^2 x 50MHz = 27mW. Across a 16-bit parallel bus that's 0.44W, which can exceed the microcontroller's own core power.

This power is dissipated in the driving IC. That's why datasheets specify I/O power separately — actual consumption is the core power plus the I/O's CV^2f.

The formula also gives the levers for reducing it: shrink C (shorter traces, fewer receivers, low-capacitance ESD parts), lower V (3.3V to 1.8V cuts it by 3.4x), or lower f (gate the clock when not needed). If a battery-powered design draws more current than the math predicts, a clock line toggling constantly is often the CV^2f culprit.

Connecting a probe changes the waveform

A 10:1 passive probe carries 10-15pF of its own. Attach it to a 33pF trace and the load becomes 45pF, slowing the rise time by about 30%. What you're measuring is the waveform with the probe attached — not the waveform without it.

This is the source of the classic "it works with the probe on, fails with it off" symptom in a marginal design: the probe's capacitance was quietly making up for a shortfall in hold time, or damping some ringing.

To reduce the effect, use an active probe with 1pF or less of capacitance, design with the probe's capacitance already counted as part of the load, or verify behavior without a probe (via an LED, or another pin's output).

Only a short trace behaves as a capacitor

Everything above treats "capacitance" as valid over a length short enough that the whole trace sits at essentially one voltage — a lumped-element view. With a fast driver and a long trace, the trace is not a capacitor but a transmission line, and what the driver sees is not capacitance but characteristic impedance (50 ohm).

In that regime you're not "charging 50pF," you're "driving current into 50 ohm," and rise time is set by reflections rather than load capacitance. The dividing line is covered in how long before a trace becomes a transmission line.

The trace capacitance calculator computes capacitance from trace dimensions. The I/O buffer drive calculator computes rise time and power from load capacitance and driver strength.