Trace capacitance, and whether the driver can charge it

A trace runs about 1pF per centimeter

Capacitance per length is C = t_pd / Z0. A 50 ohm microstrip (6.5ps/mm) gives 0.13pF/mm, or 1.3pF per cm. An inner-layer stripline (7ps/mm) gives 1.4pF/cm, and a narrow, high-impedance (100 ohm) trace far from the plane about 0.65pF/cm.

What the trace connects to adds more (table). A 10cm trace feeding three receiver ICs (5pF each), one ESD device (3pF) and one connector (2pF) adds up to 13 + 15 + 3 + 2 = 33pF. Another 30cm of flat cable (50-100pF/m) adds 15-30pF, landing at 50-60pF.

Time to charge it

A constant-current approximation gives t = C × ΔV / I: about 20.6ns for 50pF, 3.3V and 8mA. I_OH/I_OL, however, are specified at particular output voltages. They do not guarantee constant current throughout an edge, so this calculation is not a guaranteed upper bound on rise time.

Another approximation treats the output as R_on. Assuming 50Ω from the single point V_OL = 0.4V at 8mA gives τ = 2.5ns and a 10–90% edge of about 5.5ns into 50pF. Pull-up and pull-down behaviour can differ. Propagation delay measures arrival between defined reference points; rise time measures an edge between thresholds. Adding them does not give a rise time.

The half-period is 25ns at 20MHz and 10ns at 50MHz. A 5.5ns transition alone does not establish that 50MHz fails. Check receiver thresholds, setup and hold requirements, duty cycle and driver timing at the relevant load. For loads outside the timing specification or long traces, inspect the receiver waveform using suitable IBIS and interconnect models.

If drive strength is selectable, pick the lowest setting that meets the load; stronger means more ringing, crosstalk and radiated noise.

Power is C x V^2 x f

Charging a capacitor to V dissipates 1/2·CV^2 as heat in the driver's resistance, and discharging dissipates another 1/2·CV^2. That's CV^2 per cycle, so toggling at f gives P = C x V^2 x f: 50pF x 3.3^2 x 50MHz = 27mW. A 16-bit bus is 0.44W, possibly more than the microcontroller's core power. It heats the driving IC. Here f is the number of 0→1 charging events per second on each line. The 0.44W bus total assumes all 16 lines toggle every cycle; apply each line's activity factor for ordinary data traffic.

The levers: shrink C (shorter traces, fewer receivers, low-capacitance ESD parts), lower V (3.3V to 1.8V cuts it by 3.4x), or lower f (gate unused clocks). If a battery design draws more than predicted, a constantly toggling clock is often the culprit.

Connecting a probe changes the waveform

A 10:1 passive probe carries 10-15pF. On a 33pF trace the load becomes 45pF, slowing the rise by about 30%. You are measuring the waveform with the probe attached.

"It works with the probe on" in a marginal design means the probe's capacitance is making up a hold-time shortfall or damping ringing. Use an active probe with 1pF or less, count the probe's capacitance as part of the load, or verify without a probe (via an LED or another pin).

Only a short trace behaves as a capacitor

All this assumes a lumped view, where the whole trace sits at one voltage. With a fast driver and a long trace it is a transmission line: the driver sees characteristic impedance (50 ohm) instead of capacitance, and rise time is set by reflections. The dividing line is covered in how long before a trace becomes a transmission line.

The trace capacitance calculator computes capacitance from trace dimensions; the I/O buffer drive calculator computes rise time and power from load capacitance and driver strength.