Measure 0–12V with a 3.3V ADC: divider ratio, error and acquisition time

1. Define the range and the missing requirements

Assume a signal from 0 to 12V, allowing +5% at the upper end: 12.6V. Treat 3.3V as the ADC’s nominal reference and full-scale voltage, and use 12 bits for an acquisition-time example. Source output resistance is zero in this example; add a real source resistance to the upper leg and recalculate.

Check the actual ADC’s input range, minimum reference voltage, absolute maximum ratings including power-off conditions, injection current, leakage and acquisition requirements separately. This example covers normal input up to 12.6V. Surge and miswiring protection, bandwidth, sample rate and overall accuracy remain requirements to resolve.

2. Check the upper limit with 33kΩ and 10kΩ

Choose upper resistor R_T = 33kΩ and lower resistor R_B = 10kΩ, both ±1%. With no load, V_out = V_inR_B/(R_T+R_B). Output is 2.79070V at 12V input and 2.93023V at 12.6V input.

Maximum output occurs with the upper resistor at −1% (32.67kΩ) and the lower at +1% (10.10kΩ). The opposite combination gives minimum output. Review these corners as well as the nominal ratio.

The maximum is about 325mV below nominal 3.3V. It becomes usable headroom only after checking the actual minimum reference and permitted input range. It does not establish protection when an external signal reaches an unpowered ADC.

3. Use the Thevenin equivalent for static loading

Output resistance is R_TH = 33kΩ || 10kΩ = 7.67442kΩ. At 12V input, model the divider as a 2.79070V source in series with this resistance to calculate a static load separately.

For an assumed 1MΩ resistive load, V_loaded = 2.79070 × 1M/(1M+7.67442k) = 2.76944V. That is about 21.25mV, or 0.762%, below the unloaded value. This illustrates finite loading; it is not a model of a SAR ADC as a permanent 1MΩ resistor.

In a separate case with no resistive load, assume input leakage of ±100nA. The error is ±I_leakR_TH = ±0.76744mV, with direction depending on leakage polarity. This case is separate from the 1MΩ calculation. Obtain the real leakage limit, including temperature conditions, from the selected ADC.

4. Estimate acquisition with an explicitly ideal RC

For illustration only, assume a sampling capacitor C_S = 20pF, zero switch resistance, no external capacitor and a constant R_TH. To settle a full-scale step within half an LSB at 12 bits, the residual fraction must be at most 1/8192: t ≥ ln(8192)R_THC_S.

The time constant is 7.67442kΩ × 20pF = 153.49ns, giving about 1.383µs. This calculates charging an ideal capacitor from the source and divider. Neither 20pF nor these acquisition conditions specify a particular ADC. Use Microchip’s acquisition-time explanation and the selected device’s data sheet to replace them.

The 1.383µs result does not guarantee acquisition time or settling with an external RC. Real switch resistance, capacitor switching, previous-channel voltage, kickback, external capacitance and driver response can matter. Analog Devices’ SAR ADC front-end guide discusses the acquisition and input-RC design considerations.

5. Consider resistors ten times smaller

Using 3.3kΩ / 1kΩ preserves the nominal ratio and the ratio error from ±1% tolerances. Thevenin resistance falls to 767.44Ω, and acquisition in the same ideal 20pF model falls to about 0.1383µs. Divider current at 12V rises from 0.2791mA to 2.7907mA.

Lower resistance costs supply current and increases source loading. If high input resistance and short acquisition are both needed, consider a buffer, then assess its input range, output swing, capacitive-load stability, offset and current consumption. An external capacitor also needs an actual settling analysis; a larger value is not automatically better.

6. Decide with the device requirements in hand

For this normal-input calculation, 33kΩ / 10kΩ is a candidate that stays below nominal 3.3V. The next deciding information is the ADC’s input specification, acquisition settings and required accuracy. A 12-bit result does not establish 12-bit system accuracy: include resistor ratio, reference, gain, offset and leakage errors.

1. Define input limits, abnormal and power-off conditions, accuracy and bandwidth.
2. Calculate normal maximum and minimum output at resistor-tolerance corners.
3. Include source resistance, static loading and leakage, keeping error directions explicit.
4. Use the selected ADC’s model and acquisition specification, including conversion rate and channel switching.
5. On the prototype, check endpoints and intermediate voltages, then compare results with different acquisition settings and channel order.

Continue the design

Use the resistor-divider calculator for your ratio, and divider tolerance and loading for the static budget. For external RC networks and channel switching, continue to ADC input RC and kickback. Combine the RC cutoff calculator with a separate acquisition-time analysis.

Open the calculator with 12V ±5%, 33kΩ/10kΩ and ±1% resistors. This carries over the static divider inputs; sampling capacitance, acquisition time and ADC absolute maximum ratings still need separate checks.