Crystal load capacitors: how many seconds a month does 22pF off a CL of 12.5pF cost?

The Pierce oscillator and load capacitance CL: C1 and C2 alone do not decide it

Almost every crystal oscillator is a Pierce oscillator. A single inverter inside the MCU connects the two ends of the crystal, and C1 and C2 go from the XIN and XOUT pins to GND. C1 and C2 form the load the crystal sees.

The CL (load capacitance) on a crystal datasheet is the capacitance the crystal should see looking into the circuit from its two legs, and the circuit side is set by this formula.

CL = C1·C2 / (C1 + C2) + Cstray

Cstray is all the capacitance other than C1 and C2 that the legs see: MCU pin capacitance, package, and board traces and pads. The series combination of C1 and C2 plus Cstray must match the CL the crystal specifies.

The most common mistake is to buy the specified CL as the C1 and C2 values. With Cstray estimated at 3pF, the actual CL of C1 = C2 = 12.5pF is 12.5 ‖ 12.5 + 3 = 9.25pF, 3.25pF below spec. The correct approach, with C1 = C2 = C, is C/2 + Cstray = CL, so C = 2 × (CL − Cstray); for CL = 12.5pF and Cstray = 3pF, C1 = C2 = 19pF.

Where Cstray comes from

Cstray differs from board to board, so crystal datasheets do not list it. It has two main parts.

One is the MCU pin capacitance. Many MCU datasheets list C_XIN and C_XOUT, or the pin input capacitance, at about 1-3pF in the oscillator characteristics section. If a part does not list it, use the input capacitance of a similar pin (a few pF) as a guide.

The other is trace and pad capacitance. Even with the crystal and C1/C2 right beside the MCU, pads and a few mm of trace add 0.3-1pF. A trace over a solid GND plane adds more than a floating one, and if you know its length and width, the trace capacitance calculator gives an estimate.

Adding both, the estimate commonly used in practice is Cstray ≈ 2-5pF (about 3pF as a typical value), and the calculations here are based on 3pF. Whether it is really right can only be confirmed by measurement in the end (procedure below).

How much CL error moves the frequency: pulling sensitivity

The oscillation frequency f of a crystal can be written with the series resonant frequency f_s, the motional capacitance C1_m (not the same as C1 and C2), the shunt capacitance C0, and the load capacitance CL.

f / f_s = 1 + C1_m / (2·(C0 + CL))

The sensitivity S (pulling sensitivity) to a deviation of CL from the specified value is the derivative of this with respect to CL.

S = C1_m / (2·(C0 + CL)²) [ppm/pF; C1_m, C0 and CL in pF, result multiplied by 10⁶ for ppm]

A 32.768kHz tuning-fork crystal has C0 ≈ 1.0-1.5pF (typically 1.1pF) and C1_m of a few fF (typically 2fF), giving S ≈ 5.4ppm/pF at CL = 12.5pF. An MHz-range AT-cut crystal (C0 ≈ 5pF, C1_m ≈ 15fF) has a higher S, 14.2ppm/pF at CL = 18pF, but monthly clock error is mainly a problem for 32kHz parts.

S is an approximation for small changes, so for this example where CL moves by 1.5pF the f/f_s formula is used directly.

Adding 22pF to a CL of 12.5pF makes a clock about 19 seconds a month slow

Take a crystal specified for CL = 12.5pF with C1 = C2 = 22pF. The reasoning "22pF is close to twice CL (25pF) and an easy E12 value" is the classic mistake of forgetting Cstray. C1 ‖ C2 = 22 × 22 ÷ 44 = 11pF, and adding Cstray = 3pF gives an actual CL of 14.0pF, 1.5pF above spec.

Putting CL = 12.5pF (specified) and 14.0pF (actual) into the f/f_s formula and taking the difference gives Δf ≈ −7.3ppm. Multiplied by 30 days × 86400 seconds this is about −18.9 seconds, so the clock loses about 19 seconds a month. When CL is above spec (capacitors too large) the oscillation slows and the clock runs slow.

Varying Cstray over 2-5pF gives an actual CL of 13.0-16.0pF, an error of −2.6 to −15.1ppm, and a loss of 6.8-39.0 seconds a month.

The other mistake: using the specified CL directly gains about 60 seconds a month

Using the specified CL directly (C1 = C2 = 12.5pF, actual CL 9.25pF) puts CL 3.25pF below spec, so Δf ≈ +23.1ppm and the clock gains about 60 seconds a month. This is a much larger error than the 22pF mistake.

Sensitivity varies several times with the specified CL: 6pF, 7pF, 9pF and 12.5pF

The same 1.5pF error produces very different frequency errors depending on the specified CL. Since CL is in the denominator of S, the smaller the specified CL, the more sensitive the crystal. With C0 = 1.1pF and C1_m = 2fF in common, ΔCL = +1.5pF (capacitors too large) is applied to each CL.

A CL = 6pF crystal is 3.4 times as sensitive as a 12.5pF crystal to the same 1.5pF error. The lower the CL of the crystal on a board, the more carefully C1, C2 and Cstray must be chosen.

Comparison with the temperature characteristic: which dominates

A 32.768kHz tuning-fork crystal's frequency falls with the square of the temperature offset (also covered in the previous article). The calculation uses a typical coefficient of −0.034ppm/℃² and a turnover (peak-frequency temperature) of 25℃.

Δf = −0.034 × (T − 25)² [ppm]

The error from a ±10-15℃ swing typical indoors (9-20 seconds a month) is of the same order as the 22pF mistake (about 19 seconds a month). In outdoor or automotive use, with swings near ±25℃, the temperature characteristic dominates (55 seconds a month). A CL error is a fixed offset that goes away once corrected, while a temperature error moves with the environment, so setting CL correctly does not remove temperature drift. For high accuracy you need a temperature-compensated RTC IC.

Drive margin: raising CL makes startup harder

For the oscillator to start and keep running, the negative resistance the circuit generates must sufficiently exceed the crystal's equivalent series resistance (ESR, Rm). In practice a guideline of negative resistance ÷ ESR ≥ 5 is widely used (for example ST's AN2867), and below 5, some units stop oscillating with production spread, low temperature or low supply voltage.

The negative resistance of a Pierce oscillator is roughly |Rneg| ∝ gm ÷ (ω² × C1 × C2) (gm is the inverter's transconductance, ω = 2πf). The larger C1 and C2, the smaller the negative resistance, in inverse proportion to their product.

In the earlier example, 22pF against the correct C1 = C2 = 19pF raises the product by (22/19)² ≈ 1.34 times and cuts the negative resistance to about 75% of the original. A design that was only just at a margin of 5 falls to 3.7. Larger capacitors cause not just a frequency error but also failures to start or stop at low temperature, which show up as hard-to-reproduce early failures: no start right after power-on, or a few units not oscillating in a cold chamber.

Why choose a low-CL crystal: supply current

The oscillator charges and discharges C1 and C2 every cycle, so its current is roughly proportional to frequency × (C1 + C2). A crystal with a larger CL needs larger C1 and C2 and draws more current.

A CL = 12.5pF crystal needs C1 = C2 ≈ 19pF, while a CL = 6pF crystal with the same Cstray = 3pF needs C1 = C2 = 2 × (6 − 3) = 6pF, a difference of more than 3 times in capacitance. For a coin-cell-backed RTC, where current sets battery life, this matters.

A low-CL crystal wins on current but is sensitive to errors in C1, C2 and the Cstray estimate. A high-CL crystal is more tolerant, but draws more current and tends to need larger C1 and C2.

Tuning on real hardware

• Do not fix values by calculation alone. C1 = C2 = 2 × (CL − Cstray) is a starting point, and rounding to a standard value such as E12 already adds a few percent.
• Do not probe the oscillator node directly. Even a 10:1 probe has 10-15pF of tip capacitance, and putting it on XIN or XOUT adds a few pF to a dozen pF to Cstray itself. If the MCU has a clock output (MCO or CLKOUT), measure that through a buffer; otherwise use an ultra-low-capacitance FET probe or look only at the direction of the error.
• Average over a long time. A 1-second gate has a resolution of 1Hz, which is only about 30ppm at 32.768kHz. Comparing a divided 1PPS output with GPS 1PPS or NTP is easier for confirming monthly drift.
• Change C1 and C2 as a pair. An asymmetric change upsets the duty cycle and the balance of negative resistance, so keep C1 = C2 and vary both in steps of 1-2pF.
• Check across temperature. Check startup and frequency at both ends of the operating temperature range.

For the error you cannot trim out, the calibration register in the RTC of many MCUs (which drops pulses over an interval such as 32 seconds) is a practical software fix.

Calculators to use

Use the trace capacitance calculator to estimate stray capacitance, the capacitor code calculator to read capacitor markings, and the frequency and wavelength calculator to convert frequency and period.