Differential 100Ω is not two 50Ω traces: coupling lowers Zodd, and the real cost of swapping 90Ω and 100Ω

Coupling pulls Zodd below a single trace's Z0

Drive a differential pair with equal-amplitude, opposite-polarity signals (odd mode) and the field between the two traces becomes denser than the field between a single trace and its reference plane. The neighbor swings the other way, so the potential difference is nearly doubled. Capacitance per unit length rises, and from Z = √(L/C) the odd-mode impedance Zodd falls below the single-ended Z0.

Differential impedance is Zdiff = 2×Zodd. Even if the width gives 50Ω for a single trace, bringing a second one close pulls Zodd under 50Ω, and Zdiff under 100Ω. The stronger the coupling (the smaller the spacing), the bigger the drop. The weaker the coupling, the more the field goes to the plane, and Zdiff approaches 2×Z0.

Widening the spacing S from 1W to 2W to 3W

This uses the edge-coupled microstrip approximation (IPC-2141) from the microstrip impedance calculator, with the spacing S as a multiple of the trace width W. With dielectric thickness h = 0.1mm, width w = 0.14mm, copper t = 0.035mm (1oz) and εr = 4.3 (FR-4), the single-ended Z0 is about 51Ω.

With the same width and stackup, going from 1W to 2W moves Zdiff from 89Ω to 99Ω, a 10Ω change. At 1W it is 11% below a 100Ω spec, which can fall outside the allowed tolerance. Beyond 3W the change is gentle, and at 6W Zdiff has essentially converged to 2×Z0. Spacing levels off at 2-3W, so widening further to reach a target Zdiff does little.

The approximation is for surface edge-coupled microstrip only, and has a few percent of error depending on w/h and εr (see the range on the calculator page). Confirm the final spacing with your board maker's field solver.

Neck-down near a BGA

Where a pair escapes through a BGA ball pitch (often 0.5-0.8mm), the specified width and spacing may not fit. A "neck-down" narrows the width and spacing together, only through the section between balls. Narrowing both by the same ratio keeps the Zdiff change small, but not zero. The section is a short line of slightly different impedance.

How much that section disturbs the waveform follows the same reasoning as in when a trace becomes a transmission line. If the one-way delay of the section is 1/10 of the rise time t_r or less, the disturbance barely shows as a reflection. The length limit is ℓ = t_r ÷ (10 × tpd). With tpd ≈ 6.5ps/mm for surface microstrip, it gives the table below.

A real BGA neck-down usually spans one or two ball rows, about 1-3mm. For signals with rise times of a few hundred ps, like USB and LVDS, that is well under the table limit and does little harm. For signals below 100ps, like PCIe Gen4 and later, the same 1-3mm reaches or exceeds the limit. The allowed length depends on the ratio to the signal's rise time.

Three countermeasures. (1) Shorten the section: take the shortest path through the ball center. (2) Narrow only as much as needed, keeping the width-to-spacing ratio. (3) Keep the pair symmetric. If P and N detour differently, their lengths differ and skew results (see length matching).

Values by standard, and the board maker's ±10%

The specified differential impedance differs by interface. USB 2.0 uses 90Ω for both cable and traces. LVDS (TIA/EIA-644), GbE (1000BASE-T) and MIPI mostly use 100Ω, and PCI Express mostly around 85Ω. A 10-15Ω gap is a significant reflection coefficient (next section).

The values differ because each standard fits them to its other elements: connectors, cables, and the driver and receiver IC impedances. The board is normally matched to the standard's value.

When you order impedance control, the board maker's tolerance is typically ±10% of nominal (±5% costs more). Design on the basis that a 100Ω target lands anywhere in 90-110Ω, and a 90Ω target in 81-99Ω. A calculated value exactly on spec can fall outside it by the spread, so leave margin so that ±10% still fits the allowed range.

Reflection when 90Ω and 100Ω are swapped

Here is the reflection from the reflection coefficient when the trace impedance differs from the spec. Γ = (Z_actual − Z_spec) ÷ (Z_actual + Z_spec).

Routing a 100Ω interface at 90Ω gives Γ = (90−100)/(90+100) ≈ −5.3%. For a 400mV differential swing (like USB2.0 HS), the reflected amplitude is about −21mV. Routing a 90Ω USB interface at 100Ω gives Γ ≈ +5.3%, about +21mV: same size, opposite sign.

Fabrication spread of ±10% worsens the worst case. A trace meant for 90Ω that comes out at the 81Ω lower limit and is used on a 100Ω interface gives Γ = (81−100)/(81+100) ≈ −10.5% (about −42mV). A trace meant for 100Ω that comes out at 110Ω and is used on a 90Ω interface (USB) gives Γ = (110−90)/(110+90) ≈ +10.0%.

Return loss RL = −20×log10(|Γ|) is larger when the reflection is smaller. A nominal swap gives the 25dB range, and a worst case with spread drops to about 20dB. The reflection is not only from this one point: every mismatch along the path (connectors, cables, vias) adds up at the receiver, so a small Γ at one spot still counts across the whole path.

When the damage is small, and when it is not

• Small damage. (1) The mismatched section is short (a few percent of the trace, or under 1/10 of the rise time in one-way delay). (2) Slow signals, or uses like I2C and SPI with no eye-mask or return-loss test. (3) A nominal swap that stays inside the allowed range (USB 2.0 is 90Ω±15% = 76.5-103.5Ω, so a nominal 100Ω trace is inside).
• Significant damage. (1) The standard has a compliance test such as differential return loss, and you need certification or interoperability. (2) A long cable or connector follows the mismatch, and the reflection further erodes eye margin. (3) Fabrication spread stacks the wrong way and exceeds the range (110Ω on a USB 90Ω interface exceeds the 103.5Ω limit). (4) There are several mismatches on the path, and reflections accumulate.
• Telling them apart on hardware. A TDR reads the mismatch position and Γ directly. Without one, look at the eye diagram's jitter and amplitude margin. If more than half the margin remains, some reflection is absorbed, but a design at the limit fails with the very reflection computed here.

A few ohms to 10Ω off spec does not stop a circuit working at once. The problem starts when the test or eye margin is used up.

Weaker coupling lowers skew and common-mode tolerance

Widening the spacing weakens coupling, and Zdiff approaches 2×Z0, but tolerance to skew (the P-N arrival time difference) drops. In a strongly coupled pair the two propagation velocities pull toward each other, so a small length difference shifts timing less. With weak coupling the same length difference shows up as skew more directly (see length matching for tolerances).

Common-mode noise tolerance drops too. If both traces pick up the same noise in the same phase, the receiver's differential amplifier cancels it (common-mode rejection). This holds better when the traces are close, on the same layer, with the same neighbors and return path. Wider spacing makes the P and N environments differ, and part of the common-mode signal converts to differential (mode conversion).

Widening the spacing to approach the spec Zdiff therefore lowers both tolerances. Spacing is a trade-off among the spec Zdiff, the minimum fabricable width, and the allowed skew and EMI.

Where it goes wrong on real boards

A stackup change moves Zdiff. When the board maker or lot changes the dielectric thickness or permittivity, the same width and spacing give a different Zdiff, so recalculate the rules. Surface and inner layers differ too, so recompute the spacing for each layer.

Matching only the board's Zdiff is not enough: a connector or flat cable of different impedance reflects there. Check the whole path: PCB, connector, cable, connector, PCB.

Detouring only the P trace around a part, or adding a via on one side, makes that section behave single-ended, disturbs Zodd and coupling, and adds skew. Detour both traces symmetrically.

TDR measurement is the quickest check, showing the mismatch position and size in the waveform. Without one, apply the ±10% fabrication tolerance to the field-solver value and check that the worst case still fits the allowed range.