Before ordering a PCB: connect power, timing and fabrication evidence

1. Put requirements and evidence in the same worksheet

This example reviews a 1A power path and an allocation for routing delay difference. It does not specify a particular device or interface. Compare requirements, schematic, layout and fabrication data at the same revision, and assign an owner and disposition to unresolved items.

The completion conditions below are a worksheet format, not the result of a completed board review. Keep an item open when its supporting data is missing; a DRC result does not supply that evidence.

2. Calculate a 100mm copper route and vary its geometry

Assume copper resistivity at 20°C of ρ = 1.724 × 10⁻⁸Ωm and use R = ρL/(wt). For 100mm length, 0.5mm width and 35µm thickness, R = 98.514mΩ. At 1A, IR drop is 98.514mV and I²R loss is 98.514mW. This is one uniform conductor, excluding vias and contacts.

An equal return conductor doubles resistance, drop and loss. With a hypothetical 100mV allocation to the copper loop, the 0.5mm example exceeds it at 197.0mV. A 1mm-wide feed and return give 98.5mV, leaving almost no margin. These figures precede connector and via drops or increased resistance with temperature, so they do not establish acceptance.

The 0.45mm and 28µm case is an independent sensitivity assumption, not a manufacturer’s tolerance. Check temperature effects, finished copper thickness and cross-section, and the narrowest parts of the route separately. This resistance calculation does not establish ampacity or temperature rise.

3. Derive a length-difference target from a time budget

Suppose total permitted delay difference is 100ps. Conservatively reserve 20ps for package difference and 30ps for other uncertainty, leaving 50ps for PCB routing difference. For paths of the same type with an assumed delay of 6.5ps/mm, the corresponding length difference is 50 / 6.5 = 7.69mm. This is not a maximum total route length.

The 6.5ps/mm value is an assumption for this example. TI’s high-speed layout guide describes how propagation relates to dielectric and routing structure. For mixed outer and inner layers, sum delay by layer rather than relying only on the difference in physical length.

This subtraction illustrates a budgeting method. Evaluate a real interface with both setup and hold conditions, clock or strobe relationships, topology, receiver requirements, vias and package models. Do not turn 7.69mm into a general length-matching rule.

4. Hand off the assumptions as well as the files

Calculations depend on the copper and stack-up that will actually be built. Record board revision, layer order, materials, board and copper thickness, finish, holes and tolerances, and impedance requirements in the order and fabrication drawing. Make clear whether copper thickness refers to starting foil or finished copper, and whether a hole dimension is a drill size or a finished size.

As one manufacturer’s example, Eurocircuits’ mechanical-layer guide covers outline and machining information, while its tolerance table describes that supplier’s conditions. Confirm the actual service instead of transferring those values to another supplier. If impedance matters, agree a stack-up and materials with the corresponding service, as illustrated by its defined-impedance offering.

1. Freeze schematic and board revisions, and resolve or document ERC/DRC exceptions.
2. Export copper, mask, outline and drill data; inspect position, units, layer order and omissions in an independent viewer.
3. Confirm that the output preserves the power path, neckdowns and return, and the layers and lengths used in the timing budget.
4. Supply drawings and data in the manufacturer’s required formats; resolve hole, copper, tolerance and impedance interpretations.
5. Archive the exact revision sent, and review electrical and mechanical effects of any proposed manufacturing change.

5. Record the release decision

In this example, the 0.5mm copper loop exceeds the assumed 100mV allocation, while the nominal 1mm loop leaves almost no margin. Keep that item open until the path or width is revised and finished conditions are checked. The timing example corresponds to a 7.69mm difference only under its assumed common-layer conditions; it still needs actual signal specifications and stack-up data.

Retain the calculation, assumptions, open checks, owner, revision and review date. Approval applies to a particular data package and its conditions. Changes to copper thickness, stack-up or trace width can affect the electrical calculations.

Recalculate with the trace-resistance and voltage-drop calculators. Convert time and length with delay to length and length to delay. Continue to power trace width, length-matching tolerance and outer- versus inner-layer delay.