5V to 3.3V at 150mA: choose an LDO or buck from the power and thermal budgets
A regulator can meet its current rating and still be unsuitable for the board. This hypothetical 5V-to-3.3V rail turns a load list into a power budget, a thermal sensitivity check and a decision that can be reviewed before parts are ordered.
1. Write the requirements with their operating states
Assume a nominal 5V input with ±5% tolerance (4.75–5.25V), and a 3.3V output. The load currents below are illustrative design inputs, not data for particular devices. Output-voltage tolerance, ripple and start-up time remain requirements to obtain from the loads.
Assume all three loads can operate together, and first treat 150mA as continuous. Add a separate 250mA continuous case for possible expansion. A short peak needs its own duration and transient-response check; it need not have the same thermal effect as a continuous 250mA load.
| Load | Simultaneous current | Check in the real design |
|---|---|---|
| MCU | 60mA | Clock, peripherals and start-up |
| Radio | 70mA | Transmit state and burst duration |
| Sensors and other loads | 20mA | Simultaneous conversion and external supply |
| Total | 150mA | Output power: 3.3 × 0.150 = 0.495W |
2. Separate input power from regulator loss
Initially neglect the LDO quiescent current IQ. Input current is then approximately output current, and Ploss = (Vin − Vout)Iout. At 5V the input is 0.750W, the output is 0.495W and loss is 0.255W, giving 66% efficiency. Restore quiescent and other supply currents when evaluating a real part. TI’s linear-regulator guide describes the relevant selection checks.
For the buck comparison, assume 90% efficiency at this operating point. Input power is 0.495 / 0.90 = 0.550W, loss is 0.055W, and 5V input current is 110mA. Do not copy the 150mA output current to the input side. The 90% value is neither a device guarantee nor a constant to apply across the load range.
| Option | Input power | Loss | Input current |
|---|---|---|---|
| LDO, ignoring I_Q | 750mW | 255mW | 150mA |
| Buck, assumed 90% efficiency | 550mW | 55mW | 110mA |
| Buck, 85% sensitivity case | 582.4mW | 87.4mW | 116.5mA |
3. Move to the high-input thermal case
For LDO heating, use the 5.25V input limit rather than nominal input. Loss at 150mA becomes (5.25 − 3.3) × 0.150 = 0.2925W. This example holds output at 3.3V; a real worst-case check also includes output error and upper-bound supply currents in the direction that increases loss.
Take ambient temperature TA = 50°C and try effective junction-to-ambient thermal resistances θJA of 100 and 200°C/W in TJ ≈ TA + PlossθJA. As TI SPRA953D explains, θJA depends on the board and environment. These two values are model assumptions for sensitivity analysis, not package guarantees.
| Continuous load | Loss | θJA = 100°C/W | θJA = 200°C/W |
|---|---|---|---|
| 150mA | 292.5mW | 29.25°C rise → 79.25°C junction | 58.5°C rise → 108.5°C junction |
| 250mA | 487.5mW | 48.75°C rise → 98.75°C junction | 97.5°C rise → 147.5°C junction |
A calculated temperature is not itself a pass. Compare it with the selected part’s operating limits and your design margin, then validate copper, nearby heat sources, enclosure and airflow. Thermal shutdown is not a normal operating target.
4. Check low input and light load too
At the other input limit, subtract connector and trace drops from 4.75V and check the LDO’s required dropout margin. The label “5V input” does not specify the voltage at its pins. Verify the required output capacitance and ESR against the actual part’s stability conditions, including capacitance lost to DC bias and temperature.
For a buck, inspect the candidate’s efficiency data around 5V input, 3.3V output and 150mA, with the stated measurement conditions. Check light-load mode changes, ripple, inductor, capacitors and switching-current return paths. Efficiency alone does not establish acceptable analog noise or board area.
The assumed 55mW buck loss also cannot all be assigned to the IC for a junction-temperature calculation. Establish how loss is divided between the IC, inductor and other components.
5. Record the decision and what remains to verify
Under these assumptions, the buck at 90% efficiency dissipates 200mW less than the LDO at nominal input. If 250mA continuous is credible and copper area is constrained, start with a buck candidate and verify its real efficiency and implementation conditions. An LDO remains an option when 150mA is a firm limit and the board can meet the thermal, noise and area requirements.
Record input limits, continuous and peak loads, assumed efficiency, temperature conditions and unresolved requirements alongside the part rating. This example does not establish operation for an unselected device or an unmeasured board.
- List load modes and simultaneous operation; distinguish continuous current from peak duration.
- Calculate nominal input power and the current required from the source and input wiring.
- Check high input and high ambient for heating, and low input for voltage margin.
- Check actual-device current, temperature and stability conditions; use efficiency at the buck’s real operating point.
- On the prototype, check input limits, maximum continuous load, load steps, start-up and temperature in the intended enclosure; update the assumptions.
Continue the design
Enter your load in the power and efficiency calculators, then explore the synchronous buck loss calculator. Read LDO thermal resistance and copper area for the thermal assumptions, minimum on-time for operating constraints, and input-capacitor ripple current for component stress.
Frequently asked questions
Is a 300mA-rated LDO enough for 150mA?
Can I keep using 90% for buck efficiency?
Standards and references
- Texas Instruments, Tips, Tricks and Advanced Applications of Linear Regulators (SLUP415) — LDO dropout, dissipation, quiescent current and stability checks. The load list and buck efficiencies are assumptions made for this article.
- Texas Instruments, Semiconductor and IC Package Thermal Metrics (SPRA953D) — Section 1 explains the dependence of junction-to-ambient thermal resistance on test conditions and board environment.